公开(公告)号：US06801996B2

公开(公告)日：2004-10-05

申请号：US09778069

申请日：2001-02-07

申请人： Moriyasu Banno ,  Tomoaki Shoda ,  Hiroshi Itaya ,  Tomotaka Saito

发明人： Moriyasu Banno ,  Tomoaki Shoda ,  Hiroshi Itaya ,  Tomotaka Saito

IPC分类号： G06F932

CPC分类号： G06F9/30178

摘要： An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit are described. The efficiency of coding of the program is improved by making use of an existing processor as selected is used without modification. An instruction code conversion unit performs conversion of the address of a native instruction code to the address of the corresponding compressed instruction code in a program memory by shifting the address of the native instruction code as outputted from the processor to the right by one bit.

摘要翻译： 指令代码转换单元，设置有指令代码转换单元的信息处理系统和用于产生由指令代码转换单元转换的指令代码的指令代码生成方法。 通过使用未经修改地选择的现有处理器来改进程序的编码效率。 指令代码转换单元通过将从处理器输出的本地指令代码的地址向右移位一位，来执行本地指令代码的地址到程序存储器中对应的压缩指令代码的地址的转换。

公开(公告)号：US6115778A

公开(公告)日：2000-09-05

申请号：US100244

申请日：1998-06-19

申请人： Masakazu Miyake ,  Moriyasu Banno ,  Hiroyuki Watanabe

发明人： Masakazu Miyake ,  Moriyasu Banno ,  Hiroyuki Watanabe

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F13/26

CPC分类号： G06F13/24

摘要： A control system comprises an interrupt controller, having vector access signal output mechanism for outputting a vector access signal, which is activated when a start address is read out from a vector holder, and a central processing unit (CPU), comprising a present mask holder, which holds a present mask level, and a previous mask holder, which holds a previous mask level, wherein the CPU compares the interrupt level and the present mask level, and, when the interrupt level is higher than the present mask level, copies a value of the present mask level holder into the previous mask level holder, reads out a start address of an interrupt processing program corresponding to an accepted interrupt request from the vector holder, starts executing the interrupt processing program, and copies the interrupt level into a present mask level holder by means of an activated vector access signal.

摘要翻译： 控制系统包括中断控制器，具有用于输出矢量存取信号的矢量存取信号输出机构，所述矢量存取信号输出机构在从矢量保持器读出起始地址时被激活;以及中央处理单元（CPU） ，其保持当前掩码级别，以及保持先前掩码级别的先前掩码保持器，其中CPU比较中断级别和当前掩码级别，并且当中断级别高于当前掩码级别时，复制一 当前屏蔽级别保持器的值到先前的屏蔽级别保持器中，从向量保持器读出对应于接受的中断请求的中断处理程序的开始地址，开始执行中断处理程序，并将中断级别复制到现在 通过激活的向量访问信号来进行掩模级别保持。

公开(公告)号：US06959367B2

公开(公告)日：2005-10-25

申请号：US10325935

申请日：2002-12-23

申请人： Moriyasu Banno

发明人： Moriyasu Banno

IPC分类号： G06F9/30 ,  G06F9/308 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38 ,  G06F12/00 ,  G06F12/04

CPC分类号： G06F9/30018 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3885 ,  G11C7/1006

摘要： A data processing system incorporates a central processing unit to decode and execute given instructions; a memory to store given data; a bus interface unit, provided between the central processing unit and the memory, to start a read bus cycle to read data from the memory, a write bus cycle to write data to the memory, or a dummy bus cycle different from the read and write bus cycles; and a read-modify-write unit provided between the central processing unit and the bus interface unit. The read-modify-write unit includes a modify-requirements buffer to store modify requirements having modify data output from the central processing unit and an operation control signal; and a modify operation circuit to apply an operation processing to read data output from the bus interface unit with the modify data output from the modify-requirements buffer under the operation control signal to output an operation result to the bus interface unit, as write data.

摘要翻译： 数据处理系统包括中央处理单元来解码和执行给定的指令; 用于存储给定数据的存储器; 总线接口单元，设置在中央处理单元和存储器之间，以开始读取总线周期以从存储器读取数据，将写入数据写入存储器的写入总线周期或与读取和写入不同的虚拟总线周期 总线周期; 以及设置在中央处理单元和总线接口单元之间的读取 - 修改 - 写入单元。 读 - 修改 - 写单元包括修改要求缓冲器，用于存储具有从中央处理单元输出的修改数据的修改要求和操作控制信号; 以及修改操作电路，用于执行操作处理，以在由操作控制信号在修改要求缓冲器输出的修改数据中读出从总线接口单元输出的数据，以将操作结果作为写数据输出到总线接口单元。

公开(公告)号：US5680581A

公开(公告)日：1997-10-21

申请号：US364989

申请日：1994-12-28

申请人： Moriyasu Banno ,  Tatsuo Inoue

发明人： Moriyasu Banno ,  Tatsuo Inoue

IPC分类号： G06F9/32 ,  G06F12/14 ,  G06F15/78 ,  G06F21/24

CPC分类号： G06F12/1441 ,  G06F12/1433

摘要： A microcomputer has an internal program memory for storing a program and/or data, an external program memory for storing a program and/or data, a CPU for outputting a first address, for fetching an instruction stored at a location indicated by the first address from the internal program memory or the external program memory and executing the fetched instruction, and for, when the instruction instructs to read out a program or data, outputting a second address, and an internal program memory read protection circuit for receiving the first address output from the CPU and checking if the first address is present in the address space of the internal program memory, for receiving, from the CPU, the second address indicating the storage location of a program or data to be read out in accordance with the instruction and checking if the second address is present in the address space of the internal program memory. When the first address is not present in the address space of the internal program memory and the second address is present in the address space of the internal program memory, the internal program memory read protection circuit outputs a read inhibition signal to the internal program memory. The internal program memory does not execute a read access upon reception of the read inhibition signal.

摘要翻译： 微型计算机具有用于存储程序和/或数据的内部程序存储器，用于存储程序和/或数据的外部程序存储器，用于输出第一地址的CPU，用于获取存储在由第一地址指示的位置处的指令 从内部程序存储器或外部程序存储器执行取出的指令，并且当指令指示读出程序或数据时，输出第二地址，以及用于接收第一地址输出的内部程序存储器读取保护电路 从CPU检查第一地址是否存在于内部程序存储器的地址空间中，用于从CPU接收指示程序的存储位置的第二地址或要根据该指令读出的数据;以及 检查第二个地址是否存在于内部程序存储器的地址空间中。 当第一地址不存在于内部程序存储器的地址空间中，并且第二地址存在于内部程序存储器的地址空间中时，内部程序存储器读保护电路向内部程序存储器输出读禁止信号。 内部程序存储器在接收到读取禁止信号时不执行读取访问。

公开(公告)号：US5659783A

公开(公告)日：1997-08-19

申请号：US364729

申请日：1994-12-27

申请人： Moriyasu Banno

发明人： Moriyasu Banno

IPC分类号： G06F7/505 ,  G06F7/50 ,  G06F7/507 ,  G06F7/57 ,  G06F13/40 ,  G06F13/42

CPC分类号： G06F7/57 ,  G06F7/509 ,  G06F9/30036 ,  G06F2207/3828

摘要： An operation unit has operation circuits (aL, aH), temporary registers (xL, yL, xH, yH) arranged just before the operation circuits, registers (R1, R2, R3, R4) arranged if required, and data buses (d1L, d2L, d1H, d2H) for transferring data among the operation circuits, temporary registers, and registers. Data to be processed are divided, are transferred to the operation circuits through the data buses, and are simultaneously and independently processed by the operation circuits. When a result of the preceding operation affects the following operation, data except the result of the preceding operation are transferred from the registers to the temporary registers before starting the operations. These techniques shorten a processing time.

摘要翻译： 操作单元具有布置在操作电路之前的布置的寄存器（R1，R2，R3，R4）和/或数据总线（d1L，...）中的运算电路（aL，aH），临时寄存器（xL，yL，xH， d2L，d1H，d2H），用于在运算电路，临时寄存器和寄存器之间传送数据。 要处理的数据被划分，通过数据总线传送到操作电路，并由操作电路同时且独立地处理。 当上述操作的结果影响以下操作时，除了前述操作的结果之外的数据在开始操作之前从寄存器传送到临时寄存器。 这些技术缩短了处理时间。

公开(公告)号：US07408368B2

公开(公告)日：2008-08-05

申请号：US11619824

申请日：2007-01-04

申请人： Moriyasu Banno

发明人： Moriyasu Banno

IPC分类号： G01R31/02

CPC分类号： G01R31/31713 ,  G01R31/31721 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14 ,  H01L2924/00

摘要： A semiconductor device is provided with test-subject circuit 1, test-irrelevant circuit 2, first pads used for the test-subject circuit, and second pads used for the test-irrelevant circuit. The first pads include a plurality of divided pad portions while each of the second pads is provided with a single pad portion.

摘要翻译： 半导体器件设置有测试对象电路1，测试无关电路2，用于测试对象电路的第一焊盘以及用于测试无关电路的第二焊盘。 第一焊盘包括多个划分的焊盘部分，而第二焊盘中的每一个设置有单个焊盘部分。