公开(公告)号：US08767430B2

公开(公告)日：2014-07-01

申请号：US13957713

申请日：2013-08-02

Applicant: MOSAID Technologies Incorporated

Inventor： Peter Gillingham ,  Roland Schuetz

IPC: G11C5/02 ,  G11C5/00 ,  G11C5/06 ,  G11C8/00

CPC classification number: G11C5/025 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4243 ,  G11C16/04

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract translation: 可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。 响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

公开(公告)号：US20140097891A1

公开(公告)日：2014-04-10

申请号：US14101507

申请日：2013-12-10

Applicant: Mosaid Technologies Incorporated

Inventor： Roland Schuetz

IPC: H01L25/065 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C29/808 ,  H01L23/481 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Through silicon vias (TSVs) in a stacked multi-die integrated circuit package are controlled to assume different connection configurations as desired during field operation of the package in its normal mission mode. TSV connections may be reconfigured to connect an affected die in a manner different from, for example, a factory default connection of that die. TSV connections to the inputs and/or outputs of a die's native circuitry may be changed. A die may be disconnected altogether from an interface that interconnects dice in the stack, or a die that was originally disconnected from such an interface may be connected to the interface.

Abstract translation: 通过堆叠多芯片集成电路封装中的硅通孔（TSV）被控制为在其正常任务模式下在封装的现场操作期间根据需要采取不同的连接配置。 可以重新配置TSV连接以以不同于例如该管芯的工厂默认连接的方式连接受影响的管芯。 可以改变与管芯本机电路的输入和/或输出的TSV连接。 芯片可以从互连堆叠中的裸片的接口完全断开，或者原本与此接口断开连接的裸片可能连接到接口。

公开(公告)号：US08675425B2

公开(公告)日：2014-03-18

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.

Abstract translation: 存储器件和控制器的布置基于相对于已知的存储器件和控制器布置具有减少的引脚数的接口。 便利减少引脚数接口，将多个选通信号降低到单个选通信号。 此外，在数据总线上发送的分组报头后跟有效载荷，包括有效载荷的类型的编码指示。 本申请的方面涉及向传统的存储设备提供外部逻辑设备，其中逻辑设备处理单个选通和分组报头，从而允许单次选通操作。

公开(公告)号：US20130322173A1

公开(公告)日：2013-12-05

申请号：US13957713

申请日：2013-08-02

Applicant: Mosaid Technologies Incorporated

Inventor： Peter Gillingham ,  Roland Schuetz

IPC: G11C5/02 ,  G11C16/04

CPC classification number: G11C5/025 ,  G06F13/1684 ,  G06F13/4022 ,  G06F13/4243 ,  G11C16/04

Abstract: A configurable memory subsystem includes a memory module with a circuit board having a first and a second memory-containing device (MCD) pair mounted thereto. Each MCD pair has a first MCD in communication with a second MCD. Each MCD has an input port, an output port, and a memory each communicating with a bridge. In response to a command, the bridge transfers at least one of a portion of a data packet from the input port to the output port or to the memory, or transfers a portion of a memory packet from the memory to the output port. A loop-back device receives the command and the data packet form the first MCD pair and transmits the command and data packet to the second MCD pair.

Abstract translation: 可配置存储器子系统包括具有电路板的存储器模块，该电路板具有安装在其上的第一和第二存储器容纳装置（MCD）对。 每个MCD对具有与第二MCD通信的第一MCD。 每个MCD都有一个输入端口，一个输出端口和一个与桥连通的存储器。 响应于命令，桥将数据分组的一部分中的至少一个从输入端口传送到输出端口或存储器，或者将存储器分组的一部分从存储器传送到输出端口。 环回装置从第一MCD对接收命令和数据包，并将命令和数据包发送到第二MCD对。

公开(公告)号：US20130201775A1

公开(公告)日：2013-08-08

申请号：US13836702

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Roland Schuetz ,  Jin-Ki Kim

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G06F13/1689 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093

Abstract: An arrangement of memory devices and a controller is based on an interface with a reduced pin count relative to a known memory device and controller arrangement. Facilitating the reduced pin count interface the reduction of multiple strobe signal to a single strobe signal. In addition, a packet header transmitted on the data bus followed by a payload, includes an encoded indication of the type of the payload. Aspects of the present application relate to providing a traditional memory device with external logic devices, where the logic devices handle the single strobe and the packet header, thereby permitting single strobe operation.