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公开(公告)号：US20050185463A1
公开(公告)日：2005-08-25
申请号：US11058672
申请日：2005-02-16
CPC分类号： G11C16/20 , G11C16/22 , G11C2216/30
摘要： The present invention provides a nonvolatile memory which includes a card controller, a reprogrammable nonvolatile memory and an IC card chip. The card controller is capable of outputting at least one of reset response information (ATR) outputted from the IC card chip in response to a reset instruction to the IC card chip and information indicative of an erase unit of a flash memory to the outside in response to a predetermined command supplied from outside. A card host is capable of causing the card controller to change an operating speed or operating frequency or the like of the IC card chip by reference to the ATR information. Upon reprogramming of memory information with respect to the reprogrammable nonvolatile memory, the card host is capable of sending write data equivalent to an amount commensurate with an erase unit to the nonvolatile memory by reference to the information indicative of the erase unit and giving write instructions.
摘要翻译： 本发明提供一种非易失性存储器，其包括卡控制器，可再编程非易失性存储器和IC卡芯片。 卡控制器能够响应于对IC卡芯片的复位指令和指示闪存的擦除单元的信息从外部输出从IC卡芯片输出的复位响应信息（ATR）中的至少一个作为响应 到从外部提供的预定命令。 卡主机能够通过参考ATR信息使卡控制器改变IC卡芯片的操作速度或操作频率等。 在对可再编程的非易失性存储器进行存储器信息的重新编程时，卡主机能够通过参考指示擦除单元的信息并给出写指令，将与擦除单元相当的量的写入数据发送到非易失性存储器。
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公开(公告)号：US20080245878A1
公开(公告)日：2008-10-09
申请号：US12050926
申请日：2008-03-18
IPC分类号： G06K19/067
CPC分类号： G06K19/07 , G06K19/07732
摘要： Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.
摘要翻译： 公开了一种包括内置接口电路的半导体器件，其操作是响应于与其耦合的主机设备的初始化操作来选择的。 在半导体器件中，使用差分信号的第一同步接口电路和第二异步接口电路共享差分信号的外部端子（外部差分信号端子）。 例如，半导体器件采用MMC接口电路作为第一接口电路和USB接口电路作为第二接口电路，同时保持IC卡接口功能。 半导体器件专门选择所采用的接口电路的操作。 一种选择方法是在检测到从外部时钟端子输入的时钟中的多个边缘变化时启用第一接口电路的接口操作，其用于在开始向半导体器件供电时初始化第一接口电路 。
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公开(公告)号：US20070045426A1
公开(公告)日：2007-03-01
申请号：US11512126
申请日：2006-08-30
IPC分类号： G06K19/06
CPC分类号： G06F13/4239 , Y02D10/14 , Y02D10/151
摘要： The present invention is directed to suppress propagation of noise from an interface controller to an IC card microcomputer. A memory card of the invention includes an external terminal, an IC card terminal, an interface controller connected to the external terminal, a memory device connected to the interface controller, and an IC card microcomputer connected to the interface controller. The interface controller controls operation of the memory device and the IC card microcomputer in response to an input from the external terminal. The IC card terminal is directly connected to a connection line between the interface controller and the IC card microcomputer. When operation of the IC card microcomputer responding to an input from the IC card terminal is permitted in parallel with operation responding to an input from the external terminal, the interface controller sets an output buffer in the interface controller connected to the connection line into a high impedance state.
摘要翻译： 本发明旨在抑制噪声从接口控制器传播到IC卡微计算机。 本发明的存储卡包括外部端子，IC卡端子，连接到外部端子的接口控制器，连接到接口控制器的存储器件以及连接到接口控制器的IC卡微计算机。 接口控制器响应于来自外部端子的输入来控制存储器件和IC卡微计算机的操作。 IC卡终端直接连接到接口控制器和IC卡微机之间的连接线。 当响应于来自外部终端的输入的操作并行地执行响应于来自IC卡终端的输入的IC卡微计算机的操作时，接口控制器将连接到连接线的接口控制器中的输出缓冲器设置为高 阻抗状态。
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公开(公告)号：US20070136616A1
公开(公告)日：2007-06-14
申请号：US11703745
申请日：2007-02-08
IPC分类号： G06F1/00
CPC分类号： G06K19/0701 , G06K19/07
摘要： A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.
摘要翻译： 提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。 存储卡具有连接到上拉电阻的选择端子。 当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值 模式确定后的电阻值。 相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。 当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响 下拉电阻。 如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。
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5.发明授权Method of recognizing a card using a select signal during a determination mode and switching from low to high resistance after the determination 有权在确定模式期间使用选择信号识别卡并在确定之后从低电平切换到高电阻的方法公开(公告)号：US07188265B2
公开(公告)日：2007-03-06
申请号：US10716456
申请日：2003-11-20
IPC分类号： G06F1/26
CPC分类号： G06K19/0701 , G06K19/07
摘要： A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.
摘要翻译： 提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。 存储卡具有连接到上拉电阻的选择端子。 当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值 模式确定后的电阻值。 相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。 当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响 下拉电阻。 如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。
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公开(公告)号：US07708195B2
公开(公告)日：2010-05-04
申请号：US11508243
申请日：2006-08-23
CPC分类号： G06K19/077 , G06F13/4239 , G11C7/20
摘要： A memory card has external interface terminals, an interface controller connected to each of the terminals, a rewritable nonvolatile memory connected to the interface controller, and a data processor connected to the interface controller. The interface controller can perform an operation based on another command supplied from the outside in parallel with the operations of transferring a command for a data process supplied from the outside to the data processor and operating it. The interface controller has plural buffers and, after completely inputting the command for a data process from an outside to a first buffer of the plural buffers, allows data related to the other command supplied from the outside to be inputted to a second buffer of the plural buffers. The memory card can receive a command data and data to be processed subsequently from the outside without the need of waiting for the completion of the communication process between the data processor and the interface controller.
摘要翻译： 存储卡具有外部接口端子，连接到每个端子的接口控制器，连接到接口控制器的可重写非易失性存储器和连接到接口控制器的数据处理器。 接口控制器可以基于从外部向数据处理器提供的数据处理的命令的传送与数据处理器的操作并行地执行基于从外部提供的另一命令的操作并进行操作。 接口控制器具有多个缓冲器，并且在从外部向多个缓冲器的第一缓冲器完全输入数据处理命令之后，允许与从外部提供的其他命令相关的数据被输入到多个缓冲器的第二缓冲器 缓冲区 存储卡可以从外部接收要处理的命令数据和数据，而不需要等待数据处理器和接口控制器之间的通信处理的完成。
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公开(公告)号：US06917547B2
公开(公告)日：2005-07-12
申请号：US10616955
申请日：2003-07-11
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
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公开(公告)号：US07102943B2
公开(公告)日：2006-09-05
申请号：US11152101
申请日：2005-06-15
IPC分类号： G11C7/00
CPC分类号： G11C29/76 , G06F11/1068 , G11C16/04 , G11C16/3431 , G11C29/765 , G11C29/81 , G11C29/82 , G11C2029/0411
摘要： When a non-volatile memory write error occurs in a card storage device containing a non-volatile memory and an error correction circuit, write data is read from the non-volatile memory and a check is made if the error can be corrected by the error correction circuit. If the error can be corrected, the write operation is ended. If the error correction circuit cannot correct the error, substitute processing is performed to write data into some other area.
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公开(公告)号：US20070045425A1
公开(公告)日：2007-03-01
申请号：US11508243
申请日：2006-08-23
IPC分类号： G06K19/06
CPC分类号： G06K19/077 , G06F13/4239 , G11C7/20
摘要： A memory card has external interface terminals, an interface controller connected to each of the terminals, a rewritable nonvolatile memory connected to the interface controller, and a data processor connected to the interface controller. The interface controller can perform an operation based on another command supplied from the outside in parallel with the operations of transferring a command for a data process supplied from the outside to the data processor and operating it. The interface controller has plural buffers and, after completely inputting the command for a data process from an outside to a first buffer of the plural buffers, allows data related to the other command supplied from the outside to be inputted to a second buffer of the plural buffers. The memory card can receive a command data and data to be processed subsequently from the outside without the need of waiting for the completion of the communication process between the data processor and the interface controller.
摘要翻译： 存储卡具有外部接口端子，连接到每个端子的接口控制器，连接到接口控制器的可重写非易失性存储器和连接到接口控制器的数据处理器。 接口控制器可以基于从外部向数据处理器提供的数据处理的命令的传送与数据处理器的操作并行地执行基于从外部提供的另一命令的操作并进行操作。 接口控制器具有多个缓冲器，并且在从外部向多个缓冲器的第一缓冲器完全输入数据处理命令之后，允许与从外部提供的其他命令相关的数据被输入到多个缓冲器的第二缓冲器 缓冲区 存储卡可以从外部接收要处理的命令数据和数据，而不需要等待数据处理器和接口控制器之间的通信处理的完成。
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公开(公告)号：US07549086B2
公开(公告)日：2009-06-16
申请号：US11877500
申请日：2007-10-23
IPC分类号： G06F11/00
CPC分类号： G11C16/20
摘要： In the initial setting of a memory card 1, the flash check data FD stored in a flash memory 2 is read out, this data FD is compared with the operation check data FD11 stored previously in the ROM, the write check data FD12 stored in the ROM 4a is written, if a fault is not detected, to the flash memory 2, and this data is read again and is compared with the write check data. FD12 of the ROM 4a. When any fault is not detected in comparison of these data, the CPU determines that the flash memory 2 is normal. Moreover, if a fault is detected in the comparison of data, the CPU sets the reset process fault data to a register 5a to set a controller 3 to the sleep mode. When the command CMD is received during this period, data comparison is executed again.
摘要翻译： 在存储卡1的初始设置中，读出存储在闪速存储器2中的闪存检查数据FD，将该数据FD与先前存储在ROM中的操作检查数据FD11进行比较，存储在存储卡1中的写入检查数据FD12 如果没有检测到故障，ROM 4a被写入闪速存储器2，并且该数据被再次读取并且与写检查数据进行比较。 ROM 4a的FD12。 当比较这些数据时没有检测到任何故障时，CPU确定闪存2正常。 此外，如果在比较数据中检测到故障，则CPU将复位处理故障数据设置为寄存器5a，以将控制器3设置为睡眠模式。 当在此期间接收到命令CMD时，再次执行数据比较。
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