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公开(公告)号：US07683729B2
公开(公告)日：2010-03-23
申请号：US11731776
申请日：2007-03-30
IPC分类号： H03K3/282
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译： 通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。 电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。 输出时钟是转发时钟的偏斜版本。
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公开(公告)号：US20080238503A1
公开(公告)日：2008-10-02
申请号：US11731776
申请日：2007-03-30
IPC分类号： H03L7/08
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译： 通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。 电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。 输出时钟是转发时钟的偏斜版本。
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公开(公告)号：US07697601B2
公开(公告)日：2010-04-13
申请号：US11268911
申请日：2005-11-07
IPC分类号： H03H7/30
CPC分类号： H03F3/45197 , H03F3/45744
摘要： In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.
摘要翻译： 在一些实施例中，提供了在其输出处具有可控地可变偏移的均衡器电路。
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公开(公告)号：US20090086871A1
公开(公告)日：2009-04-02
申请号：US11905080
申请日：2007-09-27
IPC分类号： H04L7/00
CPC分类号： G01R31/31727 , G01R31/31726 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0074 , H03L7/06 , H03L7/24 , H04L7/0008 , H04L7/0091 , H04L25/0272
摘要： An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.
摘要翻译： 提供一种包括注入锁定振荡器和发送装置的装置。 所述注入锁定振荡器接收第一时钟信号并通过使所述第一时钟信号偏移来提供第二时钟信号。 所述发送装置接收输入信号并接收所述第二时钟信号作为时钟信号，所述发送装置基于所接收的定时信号发送输出信号。
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公开(公告)号：US09116204B2
公开(公告)日：2015-08-25
申请号：US13997604
申请日：2012-03-30
申请人： Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
发明人： Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
IPC分类号： G01R13/02 , G01R31/317 , H03K5/00
CPC分类号： G01R31/31725 , G01R25/08 , G01R31/31726 , G04F10/005 , H03K2005/00052
摘要： An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.
摘要翻译： 在集成电路（IC）芯片上构造的全数字延迟测量电路（DMC）表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。 片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值，归一化为两个时钟的时钟周期。
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公开(公告)号：US07710210B2
公开(公告)日：2010-05-04
申请号：US11905080
申请日：2007-09-27
IPC分类号： H03K3/282
CPC分类号： G01R31/31727 , G01R31/31726 , H03B5/1212 , H03B5/1228 , H03B5/1265 , H03B2200/0074 , H03L7/06 , H03L7/24 , H04L7/0008 , H04L7/0091 , H04L25/0272
摘要： An apparatus is provided that includes an injection locked oscillator and a transmitting device. The injection locked oscillator to receive a first clock signal and to provide a second clock signal by skewing the first clock signal. The transmitting device to receive an input signal and to receive the second clock signal as a clocking signal, the transmitting device to transmit an output signal based on the received clocking signal.
摘要翻译： 提供一种包括注入锁定振荡器和发送装置的装置。 所述注入锁定振荡器接收第一时钟信号并通过使所述第一时钟信号偏移来提供第二时钟信号。 所述发送装置接收输入信号并接收所述第二时钟信号作为时钟信号，所述发送装置基于所接收的定时信号发送输出信号。
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公开(公告)号：US20140203798A1
公开(公告)日：2014-07-24
申请号：US13997604
申请日：2012-03-30
申请人： Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
发明人： Frank O'Mahony , Bryan K. Casper , Mozhgan Mansuri
IPC分类号： G01R31/317
CPC分类号： G01R31/31725 , G01R25/08 , G01R31/31726 , G04F10/005 , H03K2005/00052
摘要： An all-digital delay measurement circuit (DMC) constructed on an integrated circuit (IC) die characterizes clocking circuits such as full phase rotation interpolators, also constructed on the IC die. The on-die all-digital DMC produces a digital output value proportional to the relative delay between two clocks, normalized to the clock period of the two clocks.
摘要翻译： 在集成电路（IC）芯片上构造的全数字延迟测量电路（DMC）表征了也在IC芯片上构造的诸如全相位旋转内插器的时钟电路。 片上全数字DMC产生与两个时钟之间的相对延迟成比例的数字输出值，归一化为两个时钟的时钟周期。
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公开(公告)号：US07961039B2
公开(公告)日：2011-06-14
申请号：US12536224
申请日：2009-08-05
申请人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
发明人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
IPC分类号： H03B1/00
CPC分类号： H03K5/1565 , H03H11/1291 , H03K5/01 , H03K5/1252 , H04L7/027
摘要： Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.
摘要翻译： 一些实施例包括可调谐带通滤波器以提供经滤波的输出信号; 电路部分，用于响应于滤波的输出信号提供输出信号; 比较器电路，用于响应于来自电路部分的输出信号提供比较信号; 以及响应于由比较器电路提供的比较信号来调谐可调谐带通滤波器的反馈电路。 描述和要求保护其他实施例。
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公开(公告)号：US20090289700A1
公开(公告)日：2009-11-26
申请号：US12536224
申请日：2009-08-05
申请人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
发明人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
IPC分类号： H03B1/00
CPC分类号： H03K5/1565 , H03H11/1291 , H03K5/01 , H03K5/1252 , H04L7/027
摘要： Some embodiments include a tunable bandpass filter to provide a filtered output signal; a circuit portion to provide an output signal in response to the filtered output signal; a comparator circuit to provide a comparison signal in response to the output signal from the circuit portion; and a feedback circuit to tune the tunable bandpass filter in response to the comparison signal provided by the comparator circuit. Other embodiments are described and claimed.
摘要翻译： 一些实施例包括可调谐带通滤波器以提供经滤波的输出信号; 电路部分，用于响应于滤波的输出信号提供输出信号; 比较器电路，用于响应于来自电路部分的输出信号提供比较信号; 以及响应于由比较器电路提供的比较信号来调谐可调谐带通滤波器的反馈电路。 描述和要求保护其他实施例。
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公开(公告)号：US07573326B2
公开(公告)日：2009-08-11
申请号：US11323310
申请日：2005-12-30
申请人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
发明人： Bryan K. Casper , Timothy Hollis , James E. Jaussi , Stephen R. Mooney , Frank O'Mahony , Mozhgan Mansuri
IPC分类号： H03B1/00
CPC分类号： H03K5/1565 , H03H11/1291 , H03K5/01 , H03K5/1252 , H04L7/027
摘要： A tunable bandpass filter to provide a filtered differential clock signal in response to an input differential clock signal, where an embodiment comprises a transistor pair loaded by tunable loads, and a feedback circuit to tune the tunable loads. In some embodiments, the feedback circuit tunes the loads to maximize a small-signal differential gain. In other embodiments, the feedback circuit tunes the loads to minimize a metric indicative of jitter in the filtered differential clock signal. Other embodiments are described and claimed.
摘要翻译： 一种可调谐带通滤波器，用于响应于输入差分时钟信号提供经滤波的差分时钟信号，其中实施例包括由可调谐负载加载的晶体管对，以及用于调谐可调负载的反馈电路。 在一些实施例中，反馈电路调谐负载以最大化小信号差分增益。 在其他实施例中，反馈电路调整负载以最小化指示经滤波的差分时钟信号中的抖动的度量。 描述和要求保护其他实施例。
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