公开(公告)号：US06563162B2

公开(公告)日：2003-05-13

申请号：US10102312

申请日：2002-03-19

申请人： Myoung-Hee Han ,  Young-Hoon Park ,  Ju-Wan Kim ,  Ju-Bum Lee

发明人： Myoung-Hee Han ,  Young-Hoon Park ,  Ju-Wan Kim ,  Ju-Bum Lee

IPC分类号： H01L1304

CPC分类号： H01L27/10855 ,  H01L21/76897 ,  H01L23/5222 ,  H01L27/10885 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device for reducing parasitic bit line capacitance and a method of fabricating the same are provided. The semiconductor memory device includes a conductive pad formed on a semiconductor substrate and a first interlayer insulating layer having a first contact hole that exposes the conductive pad. The first interlayer insulating layer is formed on the conductive pad and the semiconductor substrate. Bit line stacks are formed on the first interlayer insulating layer. Bit line spacers are formed from a combination of materials having different dielectric constants on the sidewalls of the bit line stack to reduce the parasitic bit line capacitance. Preferably, the bit line spacers are stack layers including silicon nitride, silicon oxide, and silicon nitride. A second interlayer insulating layer having a second contact hole is formed on the bit line stack. A conductive plug fills the first and second contact holes. A storage electrode of a capacitor is formed on the conductive plug to be connected to the conductive pad.

公开(公告)号：US06982223B2

公开(公告)日：2006-01-03

申请号：US10413944

申请日：2003-04-15

申请人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

发明人： Ju-Wan Kim ,  Shin-Hye Kim ,  Ju-Bum Lee ,  Hyong-Soo Kim

IPC分类号： H01L21/4763 ,  H01L21/31

CPC分类号： H01L21/02129 ,  H01L21/02271 ,  H01L21/02315 ,  H01L21/02337 ,  H01L21/31625 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837

摘要： A method of manufacturing a semiconductor device by which a generation of a void is prevented after depositing an interlayer dielectric material. First, a plurality of conductive patterns are formed on a substrate and then, a capping insulation layer is formed on the conductive patterns. The capping insulation layer is treated with plasma, and an interlayer dielectric material is deposited on the plasma treated capping insulation layer. The dependency of the interlayer dielectric on the type of material and form of an underlying layer is reduced to improve a gap-filling characteristic, especially for a gap having a high aspect ratio. An improved gap-filling characteristic is accomplished and the formation of all or substantially all of the voids from forming in a gap is prevented even though an interlayer dielectric is deposited under a conventional deposition conditions.

摘要翻译： 一种制造半导体器件的方法，其中在沉积层间电介质材料之后防止产生空隙。 首先，在基板上形成多个导电图案，然后在导电图案上形成封盖绝缘层。 用等离子体处理封盖绝缘层，并且在等离子体处理的封盖绝缘层上沉积层间电介质材料。 层间电介质对材料类型和下层的形式的依赖性被降低以改善间隙填充特性，特别是对于具有高纵横比的间隙。 实现了改进的间隙填充特性，并且即使在常规沉积条件下沉积层间电介质，也可防止在间隙中形成全部或基本上所有空隙的形成。

公开(公告)号：US20080020594A1

公开(公告)日：2008-01-24

申请号：US11827777

申请日：2007-07-13

申请人： Do-Hyung Kim ,  Ju-Bum Lee

发明人： Do-Hyung Kim ,  Ju-Bum Lee

IPC分类号： H01L21/31

CPC分类号： H01L45/1683 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144

摘要： In a method of manufacturing a phase-changeable memory device, a lower electrode is formed on a substrate. Silicon oxynitride is then deposited on the lower electrode at a temperature of about 450° C. to about 650° C. to form an insulating interlayer that is relatively dense on the lower electrode. The insulating interlayer is partially etched to form a contact hole exposing the lower electrode. A phase-changeable material layer pattern filling up the contact hole is formed on the insulating interlayer such that the phase-changeable material layer pattern makes contact with the lower electrode.

摘要翻译： 在制造相变存储器件的方法中，在基片上形成下电极。 然后在约450℃至约650℃的温度下将氮氧化硅沉积在下电极上，以形成在下电极上相对致密的绝缘中间层。 部分地蚀刻绝缘中间层以形成暴露下电极的接触孔。 在绝缘中间层上形成填充接触孔的相变材料层图案，使得相变材料层图案与下电极接触。

公开(公告)号：US07125774B2

公开(公告)日：2006-10-24

申请号：US10937532

申请日：2004-09-08

申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L21/3205

CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20060073669A1

公开(公告)日：2006-04-06

申请号：US11245367

申请日：2005-10-05

申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Min Kim

IPC分类号： H01L21/20

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/91

摘要： In one embodiment, to fabricate a semiconductor device, a first insulation interlayer is formed on a substrate. A contact pad is formed through the first insulation interlayer. An etch stop layer and a second insulation interlayer are sequentially formed on the first insulation interlayer and the pad. A contact hole exposing at least a portion of the contact pad is formed by partially etching the second insulation interlayer and the etch stop layer. A preliminary lower electrode is formed in the hole. The preliminary lower electrode is isotropically etched to form a lower electrode contacting the contact pad. A dielectric layer and an upper electrode are sequentially formed on the lower electrode.

摘要翻译： 在一个实施例中，为了制造半导体器件，在衬底上形成第一绝缘中间层。 通过第一绝缘夹层形成接触垫。 在第一绝缘夹层和衬垫上依次形成蚀刻停止层和第二绝缘中间层。 通过部分蚀刻第二绝缘夹层和蚀刻停止层来形成暴露接触焊盘的至少一部分的接触孔。 在孔中形成初级下电极。 预备下电极被各向同性地蚀刻以形成接触接触垫的下电极。 电介质层和上电极依次形成在下电极上。

公开(公告)号：US20050054163A1

公开(公告)日：2005-03-10

申请号：US10937532

申请日：2004-09-08

申请人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

发明人： Min Kim ,  Ju-Bum Lee ,  Hyeon-Deok Lee ,  Seung-Jae Lee

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

摘要： A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

摘要翻译： 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20110101467A1

公开(公告)日：2011-05-05

申请号：US12986739

申请日：2011-01-07

申请人： Kyung-Tae Jang ,  Ju-Bum Lee ,  Jae-Kyo Chung ,  Heung-Seop Song ,  Mi-Young Lee

发明人： Kyung-Tae Jang ,  Ju-Bum Lee ,  Jae-Kyo Chung ,  Heung-Seop Song ,  Mi-Young Lee

IPC分类号： H01L27/088

CPC分类号： H01L27/0688 ,  H01L27/088

摘要： A stacked semiconductor device includes a first gate structure formed on a substrate, a first insulating interlayer covering the first gate structure on the substrate, a first active pattern formed through and on the first insulating interlayer and contacting the substrate, a second gate structure formed on the first active pattern and the first insulating interlayer, a buffer layer covering the second gate structure on the first active pattern and the first insulating interlayer, a second insulating interlayer formed on the buffer layer, and a contact plug formed through the first and second insulating interlayers, which contacts with the substrate and is insulated from the second gate structure by the buffer layer. Operation failures of a transistor in the stacked semiconductor device can be reduced because the buffer layer prevents a word line from being electrically connected to the contact plug.

摘要翻译： 叠层半导体器件包括：形成在衬底上的第一栅极结构，覆盖衬底上的第一栅极结构的第一绝缘层，形成在第一绝缘中间层上并在第一绝缘中间层上并与衬底接触的第一有源图案;第二栅极结构， 第一有源图案和第一绝缘中间层，覆盖第一有源图案上的第二栅极结构和第一绝缘中间层的缓冲层，形成在缓冲层上的第二绝缘夹层，以及通过第一和第二绝缘体形成的接触塞 中间层，其与衬底接触并且通过缓冲层与第二栅极结构绝缘。 由于缓冲层防止字线电连接到接触插塞，所以可以减少层叠半导体器件中的晶体管的操作故障。

公开(公告)号：US20070120230A1

公开(公告)日：2007-05-31

申请号：US11585083

申请日：2006-10-24

申请人： Shin-Hye Kim ,  Ju-Bum Lee ,  Do-Hyung Kim

发明人： Shin-Hye Kim ,  Ju-Bum Lee ,  Do-Hyung Kim

IPC分类号： H01L21/8242 ,  H01L21/20 ,  H01L23/58 ,  H01L21/31

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31111 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/91

摘要： In a layer structure, a method of forming the layer structure, a method of manufacturing a capacitor having the layer structure and a method of manufacturing a semiconductor device having the capacitor, a structure may be formed on a substrate. A first insulation layer including at least one kind of impurities may be formed on the structure. A flatness of the first insulation layer may fluctuate according to the type and concentration of the impurities. The first insulation layer may include silicate glass doped with first impurities including an element in Group III and/or second impurities including an element in Group V. The flatness of the first insulation layer may improve in proportion to the concentration of the first impurities whereas in inverse proportion to the concentration of the second impurities. Accordingly, the flatness of the first insulation layer may be determined by adjusting the type and concentration of the impurities.

摘要翻译： 在层结构中，形成层结构的方法，制造具有层结构的电容器的方法以及制造具有电容器的半导体器件的方法可以在基板上形成。 可以在结构上形成包括至少一种杂质的第一绝缘层。 第一绝缘层的平坦度可能根据杂质的类型和浓度而波动。 第一绝缘层可以包括掺杂有包括第III族中的元素的第一杂质的硅酸盐玻璃和/或包含第V族中的元素的第二杂质。第一绝缘层的平坦度可以与第一杂质的浓度成比例地改善，而在 与第二杂质的浓度成反比。 因此，可以通过调整杂质的种类和浓度来确定第一绝缘层的平坦度。

公开(公告)号：US07033909B2

公开(公告)日：2006-04-25

申请号：US10822378

申请日：2004-04-12

申请人： Hong-Rae Kim ,  Ju-Bum Lee ,  Min Kim

发明人： Hong-Rae Kim ,  Ju-Bum Lee ,  Min Kim

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： Methods of forming trench isolations are provided. A method includes providing a semiconductor substrate having a cell array region and a peripheral region. At least one cell trench in the cell array region and at least one peripheral trench wider than the cell trench in the peripheral region of the substrate are formed. The cell and the peripheral trenches have sidewalls. A first dielectric layer that partially fills the cell and peripheral trenches is formed over the substrate. At least one photoresist pattern that exposes at least the cell trench partially filled with the first dielectric layer is formed over the substrate. The first dielectric layer formed on the sidewalls of the exposed cell trench is etched by using the photoresist pattern as a etch mask. Subsequently, the photoresist pattern is removed. A second dielectric layer filling the cell and peripheral trenches is formed over the substrate where the photoresist pattern is removed.

摘要翻译： 提供了形成沟槽隔离的方法。 一种方法包括提供具有单元阵列区域和周边区域的半导体衬底。 形成电池阵列区域中的至少一个电池沟道和比衬底的周边区域中的电池沟槽宽的至少一个外围沟槽。 电池和外围沟槽具有侧壁。 部分填充电池和外围沟槽的第一电介质层形成在衬底上。 在衬底上形成至少一个曝光至少部分填充有第一介电层的单元沟道的光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模蚀刻形成在暴露的单元沟槽的侧壁上的第一介电层。 随后，去除光致抗蚀剂图案。 在衬底上形成填充电池和外围沟槽的第二电介质层，其中光致抗蚀剂图案被去除。

公开(公告)号：US06372672B1

公开(公告)日：2002-04-16

申请号：US09478064

申请日：2000-01-05

申请人： Do-Hyung Kim ,  Ju-Bum Lee ,  Byung-Keun Hwang

发明人： Do-Hyung Kim ,  Ju-Bum Lee ,  Byung-Keun Hwang

IPC分类号： H01L2131

CPC分类号： H01L21/3185 ,  C23C16/345 ,  H01L21/0332

摘要： A method of forming a silicon nitride layer in a semiconductor device manufacturing process. The silicon nitride layer (SixNyHz) is formed by PE-CVD technique at low temperature to have at most 0.35 hydrogen composition. The resulting silicon nitride layer has substantially no Si—H bonding as compared with a silicon nitride layer formed at high temperature, thereby reducing thermal stress variation during annealing. The resulting silicon nitride layer exhibits reduced thermal stress variation before and after deposition, preventing a popping phenomenon and reducing the stress applied to the underlying layer.

摘要翻译： 一种在半导体器件制造工艺中形成氮化硅层的方法。 氮化硅层（SixNyHz）通过PE-CVD技术在低温下形成，具有至多0.35个氢组成。 与在高温下形成的氮化硅层相比，所得到的氮化硅层基本上不具有Si-H键，从而降低退火时的热应力变化。 所得到的氮化硅层在沉积之前和之后表现出降低的热应力变化，防止弹出现象并降低施加到下层的应力。