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公开(公告)号:US12112950B2
公开(公告)日:2024-10-08
申请号:US17667667
申请日:2022-02-09
发明人: Ming-Hung Hsieh
IPC分类号: H10B43/27 , H01L21/02 , H01L21/28 , H01L21/285 , G11C8/14
CPC分类号: H01L21/28061 , H01L21/02532 , H01L21/28556 , H10B43/27 , G11C8/14
摘要: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; and a first gate stack positioned on the substrate and including: a first gate dielectric layer positioned on the substrate; a first gate protection layer positioned on the first gate dielectric layer and including titanium silicon nitride; a first work function layer positioned on the first gate protection layer; and a first gate filler layer positioned on the first work function layer.
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公开(公告)号:US11665881B2
公开(公告)日:2023-05-30
申请号:US17390405
申请日:2021-07-30
发明人: Ming-Hung Hsieh
CPC分类号: H10B12/30 , H01L29/1033 , H01L29/7827 , H10B12/03 , H10B12/485
摘要: The present disclosure relates to a memory device with a vertical field effect transistor (VFET) and a method for preparing the memory device. The memory device includes a capacitor contact disposed in a first semiconductor substrate, and a channel structure disposed over a top surface of the first semiconductor substrate. The memory device also includes a first gate structure disposed on a first sidewall of the channel structure, and a second gate structure disposed on a second sidewall of the channel structure. The second sidewall of the channel structure is opposite to the first sidewall of the channel structure. The memory device further includes a bit line contact disposed over the channel structure. The channel structure is electrically connected to a capacitor and a bit line through the capacitor contact and the bit line contact.
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公开(公告)号:US11545453B2
公开(公告)日:2023-01-03
申请号:US17234282
申请日:2021-04-19
发明人: Ming-Hung Hsieh
IPC分类号: H01L29/786 , H01L23/00
摘要: The present application discloses a semiconductor device with a barrier layer including aluminum fluoride and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a circuit layer positioned on the substrate, a pad layer positioned in the circuit layer and including aluminum and copper, a first barrier layer positioned on the pad layer and including aluminum fluoride, and a first connector positioned on the first barrier layer.
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公开(公告)号:US12107175B2
公开(公告)日:2024-10-01
申请号:US17572813
申请日:2022-01-11
发明人: Ming-Hung Hsieh
IPC分类号: H01L23/495 , H01L25/16 , H01L31/0216 , H01L31/0232 , H01L31/102 , H10B99/00
CPC分类号: H01L31/02165 , H01L25/167 , H01L31/02327 , H01L31/102 , H10B99/00
摘要: An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.
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