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    Secure fingerprint data generating device
    2.
    发明授权
    Secure fingerprint data generating device 有权

    公开(公告)号：US10727235B2

    公开(公告)日：2020-07-28

    申请号：US16048844

    申请日：2018-07-30

    申请人： NSCore, Inc.

    发明人： Tadahiko Horiuchi

    IPC分类号： H01L27/11 ,  H01L29/08 ,  H01L27/02 ,  H01L29/78 ,  H04L9/32 ,  G11C11/418 ,  G11C11/412 ,  H01L29/47 ,  G11C11/419

    摘要： It is provided a circuit for generating finger print code data comprising: plural pairs of first transistors, each of the first transistors having a source formed in the substrate, a drain formed in the substrate, a channel formed in the substrate between the source and the drain, a gate insulating layer formed on the channel, a gate electrode formed over the gate insulating layer, and an insulating sidewall formed at a side surface of the gate electrode; plural pairs of cross coupled second transistors, each of the plural pairs of cross coupled second transistors having drains and commonly connected sources, corresponding to each of the plural pairs of first transistors; and plural pairs of third transistors, each of the plural pairs of third transistors corresponding to each of the plural pairs of cross coupled second transistors.

    Nonvolatile memory device
    4.
    发明授权
    Nonvolatile memory device 有权
    非易失性存储器件

    公开(公告)号：US09159404B2

    公开(公告)日：2015-10-13

    申请号：US14190292

    申请日：2014-02-26

    申请人： NSCore, Inc.

    发明人： Tadahiko Horiuchi

    IPC分类号： G11C5/06 ,  G11C11/419

    CPC分类号： G11C11/419 ,  G11C11/41 ,  G11C14/00 ,  G11C16/0466

    摘要： A nonvolatile memory device includes a word line, four or more bit lines, three or more MIS transistors having gate nodes thereof connected to the word line, the N-th (N: positive integer) one of the MIS transistors having two source/drain nodes thereof connected to the N-th and N+1-th ones of the bit lines, respectively, a sense circuit having two nodes and configured to amplify a difference between potentials of the two nodes, and a switch circuit configured to electrically couple the N-th and N+2-th ones of the bit lines to the two nodes of the sense circuit, respectively, and to electrically couple the N+1-th one of the bit lines to a fixed potential, for any numerical number N selected to detect single-bit data stored in the N-th and N+1-th ones of the MIS transistors.

    摘要翻译： 非易失性存储器件包括字线，四个或更多个位线，三个或更多个MIS晶体管，其栅极节点连接到字线，第三（N：正整数）一个MIS晶体管具有两个源极/漏极 其节点分别连接到位线的第N和第N + 1位，具有两个节点并被配置为放大两个节点的电位之间的差异的感测电路，以及被配置为电耦合 第N和第N + 2个位线分别连接到感测电路的两个节点，并且将N + 1个位线电耦合到固定电位，对于任何数字N 被选择以检测存储在第N和第N + 1个MIS晶体管中的单位数据。