公开(公告)号：US12249589B2

公开(公告)日：2025-03-11

申请号：US17833063

申请日：2022-06-06

Applicant: Nvidia Corporation

Inventor： Dongji Xie ,  Joe Hai ,  Zhongming Wu ,  Ernesto A. Opiniano

IPC: H01L21/00 ,  H01L23/00

Abstract: Apparatus for flattening a warped ball grid array (BGA) package, including a first plate having a first surface and opposite second surface and a second plate having a first surface and opposite second surface. The first surface of the first plate and the first surface of the second plate oppose each other with a gap there-between. The gap houses the warped BGA package there-in, the warped BGA package including a package substrate with solder balls attached to a device mounting surface of the package substrate to form a BGA thereon. The gap adjustable by changing the position of the first plate or of the second plate such that a pushing force is applicable to the warped BGA package. A method of manufacturing a flattened BGA package and computer having a circuit that include the flatted BGA package are also disclosed.

公开(公告)号：US20230395559A1

公开(公告)日：2023-12-07

申请号：US17833063

申请日：2022-06-06

Applicant: Nvidia Corporation

Inventor： Dongji Xie ,  Joe Hai ,  Zhongming Wu ,  Ernesto A. Opiniano

IPC: H01L23/00

CPC classification number: H01L24/75 ,  H01L24/81 ,  H01L2224/7555 ,  H01L2224/81201

Abstract: Apparatus for flattening a warped ball grid array (BGA) package, including a first plate having a first surface and opposite second surface and a second plate having a first surface and opposite second surface. The first surface of the first plate and the first surface of the second plate oppose each other with a gap there-between. The gap houses the warped BGA package there-in, the warped BGA package including a package substrate with solder balls attached to a device mounting surface of the package substrate to form a BGA thereon. The gap adjustable by changing the position of the first plate or of the second plate such that a pushing force is applicable to the warped BGA package. A method of manufacturing a flattened BGA package and computer having a circuit that include the flatted BGA package are also disclosed.

公开(公告)号：US20250079344A1

公开(公告)日：2025-03-06

申请号：US18242316

申请日：2023-09-05

Applicant: NVIDIA CORPORATION

Inventor： Elad Mentovich ,  Dongji Xie ,  Ron Chao

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H01L25/16

Abstract: A secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (IC). The secure electronic component assembly may comprise a printed circuit board (PCB), an integrated circuit (IC) mounted on the PCB, and a security chip that is operatively coupled to the IC. The IC may comprise a plurality of solder balls operatively coupled thereto and configured for physical and electrical connection between the IC and the PCB. The security chip is configured to detect a potential tampering of the IC.

公开(公告)号：US09329227B2

公开(公告)日：2016-05-03

申请号：US13659425

申请日：2012-10-24

Applicant: Nvidia Corporation

Inventor： Dongji Xie ,  Min Woo

IPC: G01R31/26 ,  G01R31/28 ,  G01R1/04 ,  G01R31/04

CPC classification number: G01R31/2853 ,  G01R1/0408 ,  G01R31/048 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

Abstract: An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

Abstract translation: 提出了一种用于确定集成电路的球栅阵列（BGA）组件的电可靠性的装置。 组件包括具有位于其上的集成电路（IC）测试区域的测试印刷电路板（PCB）。 通孔从IC测试区域内的表面延伸穿过测试PCB。 每个通孔具有可与其电连接的IO垫或接地垫。 具有通过焊锡凸块连接的IC芯片的IC封装通过焊球连接到IC测试区域，使得每个IO焊盘通过通孔电连接到相应的一对焊球和焊料凸块。 还提出了使用该装置测试BGA的互连可靠性的方法。

公开(公告)号：US20140111242A1

公开(公告)日：2014-04-24

申请号：US13659425

申请日：2012-10-24

Applicant: NVIDIA CORPORATION

Inventor： Dongji Xie ,  Min Woo

IPC: G01R31/26

CPC classification number: G01R31/2853 ,  G01R1/0408 ,  G01R31/048 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15311

Abstract: An apparatus for determining an electrical reliability of a ball grid array (BGA) assembly of an integrated circuit is presented. The assembly comprises a testing printed circuit board (PCB) having an integrated circuit (IC) test region located thereon. Vias extend through the testing PCB from a surface to an underside thereof within the IC test region. Each via has an IO pad or ground pad electrically connectable thereto. An IC package having an IC die connected thereto by solder bumps is connected to the IC test region by solder balls, such that each of the IO pads is electrically connectable to a respective pair of the solder balls and solder bumps by the vias. A method of testing interconnection reliability of the BGA using the apparatus is also presented.

Abstract translation: 提出了一种用于确定集成电路的球栅阵列（BGA）组件的电可靠性的装置。 组件包括具有位于其上的集成电路（IC）测试区域的测试印刷电路板（PCB）。 通孔从IC测试区域内的表面延伸穿过测试PCB。 每个通孔具有可与其电连接的IO垫或接地垫。 具有通过焊锡凸块连接的IC芯片的IC封装通过焊球连接到IC测试区域，使得每个IO焊盘通过通孔电连接到相应的一对焊球和焊料凸块。 还提出了使用该装置测试BGA的互连可靠性的方法。

公开(公告)号：US20250081349A1

公开(公告)日：2025-03-06

申请号：US18242290

申请日：2023-09-05

Applicant: NVIDIA CORPORATION

Inventor： Elad Mentovich ,  Dongji Xie ,  Ron Chao ,  Ryan Albright

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/12 ,  H05K3/28

Abstract: A secure electronic component assembly is described herein for ensuring the physical integrity of an integrated circuit (IC). The secure electronic component assembly may comprise a printed circuit board (PCB), an integrated circuit (IC) mounted on the PCB, and an underfill material disposed between the IC and the PCB. The underfill material comprises a detection agent that is configured to change a state of the IC in response to exposure to an external environment, wherein the change in the state of the IC is indicative of a tamper condition.