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公开(公告)号：US08958248B2
公开(公告)日：2015-02-17
申请号：US13827880
申请日：2013-03-14
Applicant: NXP B.V.
CPC classification number: G11C16/10 , G11C7/18 , G11C11/5621 , G11C16/0433 , G11C16/0483 , G11C16/24
Abstract: Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described.
Abstract translation: 描述闪存阵列。 在一个实施例中，闪存阵列包括双晶体管（2T）和存储器单元的存储扇区。 在每个存储器扇区中，一行扇区选择晶体管被配置为使得将数据写入存储器区段中的存储器列，通过将电压施加到与行行选择晶体管无关的位线来控制。 还描述了其它实施例。
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公开(公告)号：US20240162314A1
公开(公告)日：2024-05-16
申请号：US18054614
申请日：2022-11-11
Applicant: NXP B.V.
IPC: H01L29/423 , H01L21/28 , H01L29/66 , H01L29/788
CPC classification number: H01L29/42328 , H01L29/40114 , H01L29/66825 , H01L29/7883
Abstract: A multi-time programmable memory cell is provided. The multi-time programmable memory cell includes a floating gate formed on a field oxide region formed on a semiconductor substrate. A control gate is formed on the field oxide region and located parallel to a first portion of the floating gate. A program-erase electrode is formed on the field oxide region and proximate to a second portion of the floating gate. A first well region and a second well region are formed in the semiconductor substrate such that a channel region is formed between the first well region and the second well region with a third portion of the floating gate overlaying the channel region.
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Patent Agency Ranking
公开(公告)号：US20140269075A1
公开(公告)日：2014-09-18
申请号：US13827880
申请日：2013-03-14
Applicant: NXP B.V.
IPC: G11C16/10
CPC classification number: G11C16/10 , G11C7/18 , G11C11/5621 , G11C16/0433 , G11C16/0483 , G11C16/24
Abstract: Flash memory arrays are described. In one embodiment, a flash memory array includes memory sectors of Two-Transistor (2T) AND memory cells. Within each of the memory sectors, a row of sector selection transistors is configured such that writing data onto a memory column within the memory sector is controlled by applying a voltage to a bit line, independent from the row of sector selection transistors. Other embodiments are also described.
Abstract translation: 描述闪存阵列。 在一个实施例中，闪存阵列包括双晶体管（2T）和存储器单元的存储扇区。 在每个存储器扇区中，一行扇区选择晶体管被配置为使得将数据写入存储器区段中的存储器列，通过将电压施加到与行行选择晶体管无关的位线来控制。 还描述了其它实施例。
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公开(公告)号：US20140167055A1
公开(公告)日：2014-06-19
申请号：US14098923
申请日：2013-12-06
Applicant: NXP B.V.
Inventor： Evelyne Gridelet , Hans Mertens , Michiel Jos van Duuren , Tony Vanhoucke , Viet Thanh Dinh
CPC classification number: H01L27/0623 , H01L21/8249 , H01L27/11546
Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.
Abstract translation: 公开了用于处理硅晶片的方法和系统。 一种方法包括在硅晶片中提供闪速存储区域，并在硅晶片中提供具有多晶硅外部基极的双极晶体管。 闪存区域和双极晶体管通过沉积闪存区域和双极晶体管两者共同的单个多晶硅层来形成。
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公开(公告)号：US11670394B2
公开(公告)日：2023-06-06
申请号：US17405633
申请日：2021-08-18
Applicant: NXP B.V.
Inventor： Michiel Jos van Duuren , Guido Jozef Maria Dormans , Anirban Roy
CPC classification number: G11C29/42 , G11C7/04 , G11C29/4401 , G11C2207/2254
Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.
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公开(公告)号：US20230056133A1
公开(公告)日：2023-02-23
申请号：US17405633
申请日：2021-08-18
Applicant: NXP B.V.
Inventor： Michiel Jos van Duuren , Guido Jozef Maria Dormans , Anirban Roy
Abstract: A temperature exposure detection system includes a plurality of nonvolatile memory cells. The memory includes memory read circuitry for reading the plurality of memory cells to determine a data retention error rate of the plurality of memory cells. The temperature exposure detection system determines a temperature exposure of the system based on the determined data retention error rate.
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公开(公告)号：US09269706B2
公开(公告)日：2016-02-23
申请号：US14098923
申请日：2013-12-06
Applicant: NXP B.V.
Inventor： Evelyne Gridelet , Hans Mertens , Michiel Jos van Duuren , Tony Vanhoucke , Viet Thanh Dinh
IPC: H01L21/8238 , H01L27/06 , H01L21/8249 , H01L27/115
CPC classification number: H01L27/0623 , H01L21/8249 , H01L27/11546
Abstract: Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.
Abstract translation: 公开了用于处理硅晶片的方法和系统。 一种方法包括在硅晶片中提供闪速存储区域，并在硅晶片中提供具有多晶硅外部基极的双极晶体管。 闪存区域和双极晶体管通过沉积闪存区域和双极晶体管两者共同的单个多晶硅层来形成。
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