-
公开(公告)号：US10942748B2
公开(公告)日：2021-03-09
申请号：US14800952
申请日：2015-07-16
Applicant: NXP B.V.
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
-
公开(公告)号：US08836379B2
公开(公告)日：2014-09-16
申请号：US14175822
申请日：2014-02-07
Applicant: NXP B.V.
Inventor： Surendra Guntur , Ghiath Al-kadi , Rinze Ida Mechtildis Peter Meijer , Jan Hoogerbrugge , Hamed Fatemi
Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.
Abstract translation: 本发明提供一种时钟选择电路和方法，其使用不同分支中的锁存器之间的反馈装置，每个分支用于将相关联的时钟信号耦合到电路输出。 在用于防止该反馈装置中的锁定延迟的反馈装置中的一个中提供了超控电路。 这使得能够在两个方向上的时钟之间快速切换。
-
Patent Agency Ranking
3.发明授权Cycle stealing when a process or environmental variation is detected and a processing instruction is using a critical path 有权当检测到过程或环境变化并且处理指令使用关键路径时，循环窃取公开(公告)号：US09329622B2
公开(公告)日：2016-05-03
申请号：US14244757
申请日：2014-04-03
Applicant: NXP B.V.
Inventor： Hamed Fatemi , Rinze Ida Mechtildis Peter Meijer , Ghiath Al-Kadi , Surendra Guntur , Jan Hoogerbrugge
Abstract: This invention provides a clock control circuit, which can be added to any pipeline-processor to solve timing problems arising from variations due to process outcome and environmental conditions. Critical instructions are detected (instructions that exercise critical paths) in conjunction with environmental sensing (such as process, temperature and voltage). This information is used to control cycle stealing.
Abstract translation: 本发明提供一种时钟控制电路，其可以被添加到任何流水线处理器以解决由于过程结果和环境条件引起的变化引起的定时问题。 检测到关键指令（执行关键路径的指令）与环境感测（如过程，温度和电压）相结合。 此信息用于控制周期窃取。
-
公开(公告)号：US20150372666A1
公开(公告)日：2015-12-24
申请号：US14718294
申请日：2015-05-21
Applicant: NXP B.V.
Inventor： Juan Echeverri Escobar , Surendra Guntur , Manvi Agarwal , Rinze Ida Mechtildis Peter Meijer
IPC: H03K5/13
CPC classification number: G01R31/31725 , G01R31/31727 , G01R31/31937 , H03K3/0375
Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.
Abstract translation: 集成电路包括：第一处理级，包括用于对输入信号执行处理操作的处理逻辑，以产生输出信号，其中输入信号对应于先前处理级的输出信号; 第一采样元件，适于与时钟信号同步地采样所述输出信号的第一值; 第二采样元件，适于与第一延迟时钟信号同步地采样所述输出信号的第二值; 以及第一延迟时钟信号发生器，其适于响应于在所述先前处理级中产生的控制信号选择性地产生所述第一延迟时钟信号。
-
公开(公告)号：US20170017486A1
公开(公告)日：2017-01-19
申请号：US14800952
申请日：2015-07-16
Applicant: NXP B.V.
IPC: G06F9/30
CPC classification number: G06F9/3005 , G06F9/30098 , G06F9/30123 , G06F9/30134 , G06F9/30181 , G06F9/327 , G06F9/3836 , G06F9/3857 , G06F9/3867 , G06F9/3885
Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.
Abstract translation: 在一个实施例中，公开了一种用于处理微控制器中的指令的方法。 在本实施例中，该方法涉及在执行指令时接收到中断，完成阴影功能单元完成指令的执行，并且在服务中断时终止重新执行指令并更新主寄存器文件 由阴影功能单元执行指令的结果。
-
6.发明授权Integrated circuit control based on a first sample value and a delayed second sample value 有权基于第一采样值和延迟的第二采样值的集成电路控制公开(公告)号：US09488691B2
公开(公告)日：2016-11-08
申请号：US14718294
申请日：2015-05-21
Applicant: NXP B.V.
Inventor： Juan Echeverri Escobar , Surendra Guntur , Manvi Agarwal , Rinze Ida Mechtildis Peter Meijer
IPC: G01R31/28 , G01R31/317 , G01R31/3193 , H03K3/037
CPC classification number: G01R31/31725 , G01R31/31727 , G01R31/31937 , H03K3/0375
Abstract: An integrated circuit comprises: a first processing stage comprising processing logic for performing a processing operation on an input signal to generate an output signal, wherein the input signal corresponds to an output signal of a previous processing stage; a first sampling element adapted to sample a first value of said output signal synchronously with a clock signal; a second sampling element adapted to sample a second value of said output signal synchronously with a first delayed clock signal; and a first delayed clock signal generator, adapted to selectively generate said first delayed clock signal in response to a control signal generated in said previous processing stage.
Abstract translation: 集成电路包括：第一处理级，包括用于对输入信号执行处理操作以产生输出信号的处理逻辑，其中所述输入信号对应于先前处理级的输出信号; 第一采样元件，适于与时钟信号同步地采样所述输出信号的第一值; 第二采样元件，适于与第一延迟时钟信号同步地采样所述输出信号的第二值; 以及第一延迟时钟信号发生器，其适于响应于在所述先前处理级中产生的控制信号选择性地产生所述第一延迟时钟信号。
-
公开(公告)号：US20140223220A1
公开(公告)日：2014-08-07
申请号：US14175822
申请日：2014-02-07
Applicant: NXP B.V.
Inventor： Surendra Guntur , Ghiath Al-kadi , Rinze Ida Mechtildis Peter Meijer , Jan Hoogerbrugge , Hamed Fatemi
IPC: G06F1/08
Abstract: The invention provides a clock select circuit and method which uses feedback arrangements between latches in different branches, with each branch for coupling an associated clock signal to the circuit output. An override circuit is provided in one of the feedback arrangements for preventing a latching delay in that feedback arrangement. This enables rapid switching between clocks in both directions.
Abstract translation: 本发明提供一种时钟选择电路和方法，其使用不同分支中的锁存器之间的反馈装置，每个分支用于将相关联的时钟信号耦合到电路输出。 在用于防止该反馈装置中的锁定延迟的反馈装置中的一个中提供了超控电路。 这使得能够在两个方向上的时钟之间快速切换。
-
-
-
-
-
-
Search Results
7
records
(took 0.013 seconds)
