-
公开(公告)号：US10785650B2
公开(公告)日：2020-09-22
申请号：US15898304
申请日：2018-02-16
Applicant: NXP B.V.
Inventor： Jan Dutz , Wolfgang Küchler , Frank Leong , Thomas Baier , Arie Geert Cornelis Koppelaar
IPC: H04W12/08 , H04L5/00 , H04W64/00 , H04B7/06 , H04L27/00 , H04B7/08 , H04W12/10 , H04L7/04 , G07C9/00 , H04W12/12 , H04W12/00
Abstract: A processing module for a receiver device is disclosed. The processing module is configured to provide for processing of a signal received by the receiver device from a transmitter device. The signal includes a secure training sequence divided into a plurality of time spaced blocks. The secure training sequence incoudes a non-repeating pattern of symbols. The processing module is configured to, based on a first phase marker in the first block and a second phase marker in the second block defining a phase difference of the signal between the first and second antennas and a known spacing of the first antenna relative to the second antenna, determine an angle of arrival of the signal relative to the receiver device.
-
公开(公告)号：US20190074930A1
公开(公告)日：2019-03-07
申请号：US16029462
申请日：2018-07-06
Applicant: NXP B.V.
Inventor： Wolfgang Küchler , Ghiath Al-kadi , Thomas Baier , Jan Dutz
Abstract: The disclosure relates to a processing module of a receiver device and associated method and apparatus. The method comprises receiving a signal comprising one or more frames, each frame comprising a synchronization-symbol-portion, a security-sequence-portion, and a data-payload-portion; and processing the signal to perform carrier recovery, and excluding at least part of the security-sequence-portions of the one or more frames from the carrier recovery process.
-
公开(公告)号：US10530529B2
公开(公告)日：2020-01-07
申请号：US16029462
申请日：2018-07-06
Applicant: NXP B.V.
Inventor： Wolfgang Küchler , Ghiath Al-kadi , Thomas Baier , Jan Dutz
Abstract: The disclosure relates to a processing module of a receiver device and associated method and apparatus. The method comprises receiving a signal comprising one or more frames, each frame comprising a synchronization-symbol-portion, a security-sequence-portion, and a data-payload-portion; and processing the signal to perform carrier recovery, and excluding at least part of the security-sequence-portions of the one or more frames from the carrier recovery process.
-
公开(公告)号：US10715355B2
公开(公告)日：2020-07-14
申请号：US15611014
申请日：2017-06-01
Applicant: NXP B.V.
Inventor： Thomas Baier , Wolfgang Küchler , Frank Leong
Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.
-
公开(公告)号：US10298337B2
公开(公告)日：2019-05-21
申请号：US15697073
申请日：2017-09-06
Applicant: NXP B.V.
Inventor： Wolfgang Küchler , Thomas Baier , Manuel Lafer
Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the validation pattern to generate channel estimate validation information.
-
Patent Agency Ranking
公开(公告)号：US20160112028A1
公开(公告)日：2016-04-21
申请号：US14885208
申请日：2015-10-16
Applicant: NXP B.V.
Inventor： Thomas Baier , Michael Gebhart
IPC: H03H7/40 , H01Q7/00 , H01L23/495 , H01Q1/50
CPC classification number: H03H7/40 , H01L23/495 , H01L2924/0002 , H01Q1/50 , H01Q7/00 , H01L2924/00
Abstract: An apparatus and method are described for automatically matching the impedance of an antenna. An impedance matching network includes at least one variable impedance element and has an input for receiving a drive signal and an output connectable to an antenna. The impedance matching network includes a shunt capacitor in series between the input and output. A phase measuring measures the phase difference between the voltage and the current of the drive signal using the voltage drop across the shunt capacitor and outputs a measured phase signal. A voltage measuring circuit measures the magnitude of the voltage of the drive signal and the voltage drop across the shunt capacitor and outputs a measured drive voltage signal and shunt capacitor voltage signal. An automatic impedance matching circuit can output a control signal to adjust the impedance of the variable impedance element and determines the impedance of the impedance matching network from the measured phase, drive voltage and shunt capacitor voltages automatically to reduce the difference between the determined impedance of the impedance matching network and the impedance of the antenna.
Abstract translation: 描述了一种用于自动匹配天线的阻抗的装置和方法。 阻抗匹配网络包括至少一个可变阻抗元件，并且具有用于接收驱动信号的输入和可连接到天线的输出。 阻抗匹配网络包括输入和输出之间串联的并联电容器。 相位测量使用分流电容器两端的电压降来测量驱动信号的电压和电流之间的相位差，并输出测得的相位信号。 电压测量电路测量驱动信号的电压幅度和分流电容器两端的电压降，并输出测量的驱动电压信号和分流电容器电压信号。 自动阻抗匹配电路可以输出控制信号来调节可变阻抗元件的阻抗，并自动测量阻抗匹配网络的阻抗，从测量的相位，驱动电压和并联电容器电压自动减小所确定的阻抗之间的差异 阻抗匹配网络和天线的阻抗。
-
公开(公告)号：US10805092B2
公开(公告)日：2020-10-13
申请号：US15898998
申请日：2018-02-19
Applicant: NXP B.V.
Inventor： Jan Dutz , Wolfgang Küchler , Frank Leong , Thomas Baier , Arie Geert Cornelis Koppelaar
Abstract: A processing module for a first lock device of a range determination system, the range determination system comprising a lock group comprising a plurality of lock devices of which the first lock device forms part, the plurality of lock devices physically spaced over a lockable element and configured to communicate with a key group comprising a plurality of key devices, a shortest distance between any one of the key devices of the key group and any one of the lock devices of the lock group providing for access to the lockable element relative to a threshold distance.
-
公开(公告)号：US20190222443A1
公开(公告)日：2019-07-18
申请号：US16360945
申请日：2019-03-21
Applicant: NXP B.V.
Inventor： Thomas Baier , Wolfgang Küchler , Frank Leong
CPC classification number: H04L25/0202 , G01S5/0215 , G01S13/765 , H04J3/0608 , H04L7/042 , H04L7/043 , H04L9/3236 , H04L25/0212 , H04L25/0224
Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.
-
公开(公告)号：US20240313785A1
公开(公告)日：2024-09-19
申请号：US18582790
申请日：2024-02-21
Applicant: NXP B.V.
Inventor： Thomas Baier , Jan van Sinderen , Jens Fleischhacker
IPC: H03L7/081
CPC classification number: H03L7/0814 , H03L7/0818
Abstract: Embodiments of a multiphase clock generation device may include an input for feeding a reference clock, a clock generation unit adapted to generate phase-shifted clock signals from the reference clock, and a phase comparator unit functionally coupled with the clock generation unit. The phase comparator unit is adapted to measure a phase shift of the phase-shifted clock signals. The multiphase clock generation device includes a self-calibration unit that is functionally coupled with the clock generation unit. The calibration unit outputs a delay-calibration parameter to the clock generation unit. The clock generation unit is adapted to generate a multiphase clock signal out of the reference clock and the delay-calibration parameter.
-
公开(公告)号：US20240204812A1
公开(公告)日：2024-06-20
申请号：US18519033
申请日：2023-11-26
Applicant: NXP B.V.
Inventor： Thomas Baier , Jens Fleischhacker , Jan van Sinderen
CPC classification number: H04B1/1036 , H03M1/12 , H04B2001/1072
Abstract: Interferer cancellation device, including a device with an antenna input to receive a signal, wherein the signal comprises a wanted signal together with an unwanted interferer; and a feedback device, built to reconstruct the unwanted interferer interfering with the wanted signal into digital and to convert a reconstructed interferer into analog, wherein the reconstructed interferer is subtractable from the received signal at the antenna input.
-
-
-
-
-
-
-
-
-
Search Results
18
records
(took 0.026 seconds)
