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    INTRA-CHIP POWER AND TEST SIGNAL GENERATION FOR USE WITH TEST STRUCTURES ON WAFERS
    3.
    发明申请
    INTRA-CHIP POWER AND TEST SIGNAL GENERATION FOR USE WITH TEST STRUCTURES ON WAFERS 有权
    芯片功率和测试信号产生用于波形测试结构

    公开(公告)号：US20080100319A1

    公开(公告)日：2008-05-01

    申请号：US11935297

    申请日：2007-11-05

    Applicant: Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    Inventor： Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    IPC: G01R31/26

    CPC classification number: H01L22/20 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/31707 ,  G01R31/31718 ,  G01R31/318505 ,  G01R31/318511 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

    Abstract translation: 可以从晶片处于部分制造状态开始分析晶片的制造。 可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。 已知指定的性能参数指示制造中的特定制造工艺。 然后可以基于多个位置处的性能参数的值的方差来获得评估信息。 这可以在不影响从芯片产生的芯片的可用性的情况下完成。 评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

    SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP
    5.
    发明申请
    SYSTEM AND APPARATUS FOR USING TEST STRUCTURES INSIDE OF A CHIP DURING THE FABRICATION OF THE CHIP 审中-公开
    在制造芯片期间使用芯片内部的测试结构的系统和装置

    公开(公告)号：US20070236232A1

    公开(公告)日：2007-10-11

    申请号：US11763001

    申请日：2007-06-14

    Applicant: Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    Inventor： Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    IPC: G01R31/305

    CPC classification number: H01L22/20 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/31707 ,  G01R31/31718 ,  G01R31/318505 ,  G01R31/318511 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

    Abstract translation: 可以从晶片处于部分制造状态开始分析晶片的制造。 可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。 已知指定的性能参数指示制造中的特定制造工艺。 然后可以基于多个位置处的性能参数的值的方差来获得评估信息。 这可以在不影响从芯片产生的芯片的可用性的情况下完成。 评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

    TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
    7.
    发明申请
    TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER 有权
    用于评估一个DIE和WAFER的制造技术

    公开(公告)号：US20070187679A1

    公开(公告)日：2007-08-16

    申请号：US11738219

    申请日：2007-04-20

    Applicant: Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    Inventor： Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    IPC: H01L23/58

    CPC classification number: H01L22/20 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/31707 ,  G01R31/31718 ,  G01R31/318505 ,  G01R31/318511 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter of the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

    Abstract translation: 可以从晶片处于部分制造状态开始分析晶片的制造。 可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。 已知指定的性能参数指示制造中的特定制造工艺。 然后可以基于多个位置的性能参数的值的方差来获得评估信息。 这可以在不影响从芯片产生的芯片的可用性的情况下完成。 评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

    TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER
    8.
    发明申请
    TECHNIQUE FOR EVALUATING A FABRICATION OF A DIE AND WAFER 有权
    用于评估一个DIE和WAFER的制造技术

    公开(公告)号：US20070004063A1

    公开(公告)日：2007-01-04

    申请号：US11469305

    申请日：2006-08-31

    Applicant: Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    Inventor： Majid Aghababazadeh ,  Jose Estabil ,  Nader Pakdaman ,  Gary Steinbrueck ,  James Vickers

    IPC: H01L21/66 ,  H01L23/58

    CPC classification number: H01L22/20 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/31707 ,  G01R31/31718 ,  G01R31/318505 ,  G01R31/318511 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

    Abstract translation: 可以从晶片处于部分制造状态开始分析晶片的制造。 可以在晶片的管芯的有效区域上的多个位置处确定指定性能参数的值。 已知指定的性能参数指示制造中的特定制造工艺。 然后可以基于多个位置处的性能参数的值的方差来获得评估信息。 这可以在不影响从芯片产生的芯片的可用性的情况下完成。 评价信息可以用于评估执行由性能参数值指示的包括特定制造过程的一个或多个处理。

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