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1.发明授权Semiconductor device having a memory and calibration circuit that selectively adjusts an impedance of an output buffer dependent upon refresh commands 有权具有存储器和校准电路的半导体器件，其根据刷新命令有选择地调节输出缓冲器的阻抗公开(公告)号：US09043539B2
公开(公告)日：2015-05-26
申请号：US12923261
申请日：2010-09-10
申请人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
发明人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
IPC分类号： G06F12/00 , G11C7/00 , G11C11/406 , G11C7/04 , G11C7/10 , G11C7/20 , G11C11/4072 , G11C11/4093
CPC分类号： G11C11/406 , G11C7/04 , G11C7/1057 , G11C7/20 , G11C11/40611 , G11C11/40626 , G11C11/4072 , G11C11/4093 , G11C2207/2254 , G11C2211/4061
摘要： A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.
摘要翻译： 一种具有选择性地调节输出缓冲器的阻抗的电路的半导体器件。 可以自动执行校准操作，而不从控制器发出校准命令。 由于响应于已经发出预定次数的自动刷新命令执行对存储器的校准操作，因此可以确保周期性校准操作，并且在期间不会从控制器请求读取操作或写入操作 校准操作。 当刷新计数器指示预定值时，启动电路激活校准电路，并且当校准电路被激活时，响应于自动刷新命令禁止刷新操作。 可以使用温度检测电路来改变执行校准操作的频率。
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2.发明申请Semiconductor device having calibration circuit that adjusts an impedance of output buffer and data processing system including the same 有权具有调整输出缓冲器的阻抗的校准电路的半导体器件及包括该校正电路的数据处理系统公开(公告)号：US20110066798A1
公开(公告)日：2011-03-17
申请号：US12923261
申请日：2010-09-10
申请人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
发明人： Nakaba Kaiwa , Yutaka Ikeda , Hiroki Fujisawa , Tetsuaki Okahiro
CPC分类号： G11C11/406 , G11C7/04 , G11C7/1057 , G11C7/20 , G11C11/40611 , G11C11/40626 , G11C11/4072 , G11C11/4093 , G11C2207/2254 , G11C2211/4061
摘要： A calibration operation can be performed automatically at a semiconductor device without issuing a calibration command from a controller. Because a calibration operation is performed in response to a fact that the auto refresh command has been issued for a predetermined number of times, a periodical calibration operation can be secured and a read operation or a write operation is not requested from a controller during a calibration operation.
摘要翻译： 可以在半导体装置处自动执行校准操作，而不从控制器发出校准命令。 由于响应于自动刷新命令已经发出预定次数的事实执行校准操作，所以可以确保周期性校准操作，并且在校准期间不从控制器请求读取操作或写入操作 操作。
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3.发明授权公开(公告)号：US08804446B2
公开(公告)日：2014-08-12
申请号：US13280949
申请日：2011-10-25
申请人： Tetsuaki Okahiro
发明人： Tetsuaki Okahiro
IPC分类号： G11C7/00
CPC分类号： G11C11/4085 , G11C7/08 , G11C8/08 , G11C8/14 , G11C11/4091 , G11C11/4094
摘要： A semiconductor device includes: a sense amplifier including an equalizing circuit that equalizes a pair of bit lines; an equalizing control circuit that converts the amplitude of an equalizing signal into a VDD level, and a word driver that controls a sub word line based on a timing signal. The word driver includes a level shift circuit for changing the operation timing of the sub word line in accordance with the VDD level, allowing a timing to complete the equalizing operation and a timing to reset the sub word line to synchronize even when the level of the VDD level is changed.
摘要翻译： 一种半导体器件包括：读出放大器，包括均衡一对位线的均衡电路; 均衡控制电路，其将均衡信号的幅度转换为VDD电平;以及字驱动器，其基于定时信号控制子字线。 字驱动器包括电平移位电路，用于根据VDD电平改变子字线的操作定时，允许定时完成均衡操作和定时以使子字线重置以使即使当 VDD电平改变。
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公开(公告)号：US08451677B2
公开(公告)日：2013-05-28
申请号：US13586526
申请日：2012-08-15
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G11C11/406 , G11C16/3418 , G11C29/783
摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。
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公开(公告)号：US08274855B2
公开(公告)日：2012-09-25
申请号：US13168804
申请日：2011-06-24
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G11C11/406 , G11C16/3418 , G11C29/783
摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。
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公开(公告)号：US08068375B2
公开(公告)日：2011-11-29
申请号：US12353622
申请日：2009-01-14
IPC分类号： G11C7/00
CPC分类号： G11C11/408 , G11C11/406 , G11C16/3418 , G11C29/783
摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。
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公开(公告)号：US20100128548A1
公开(公告)日：2010-05-27
申请号：US12353622
申请日：2009-01-14
CPC分类号： G11C11/408 , G11C11/406 , G11C16/3418 , G11C29/783
摘要： A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by the address scrambling circuit. This structure makes it possible to completely refresh operation concerned with normal word lines and redundancy word lines.
摘要翻译： 根据本发明的半导体器件具有用于执行地址的地址加扰操作的地址加扰电路和用于判断对由地址加扰电路加扰的地址执行冗余判断的冗余判定电路。 该结构使得可以完全刷新与正常字线和冗余字线有关的操作。
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8.发明授权Semiconductor memory device capable of matching the timing between sub-amplifier control signal and column selection signal 失效半导体存储器件能够匹配子放大器控制信号和列选择信号之间的定时公开(公告)号：US08391085B2
公开(公告)日：2013-03-05
申请号：US12605755
申请日：2009-10-26
申请人： Tetsuaki Okahiro , Hiromasa Noda , Jun Suzuki
发明人： Tetsuaki Okahiro , Hiromasa Noda , Jun Suzuki
IPC分类号： G11C7/22
CPC分类号： G11C7/18
摘要： A semiconductor memory device comprises a plurality of memory cell mats, a plurality of sub-word driver regions and a plurality of sense amplifier regions, a plurality of intersection regions, a sub-amplifier, and a start signal (a control signal) supply circuit (a sub-amplifier control circuit). A plurality of sub-word driver regions and a plurality of sense amplifier regions are disposed adjacent to the plurality of memory cell mats. A plurality of intersection regions are intersection regions between the plurality of sub-word driver regions and the plurality of sense amplifier regions. The sub-amplifier is disposed in a first intersection region among the plurality of intersection regions. The start signal supply circuit is disposed in a second intersection region among the plurality of intersection regions, and supplies a start signal (a control signal) of the sub-amplifier to the sub-amplifier based on a sub-amplifier timing signal supplied from the extending direction of the sub-word driver region.
摘要翻译： 半导体存储器件包括多个存储单元阵列，多个子字驱动器区域和多个读出放大器区域，多个交叉区域，子放大器和起始信号（控制信号）供给电路 （子放大器控制电路）。 多个子字驱动器区域和多个读出放大器区域被布置为与多个存储单元垫相邻。 多个交叉区域是多个子字驱动器区域和多个读出放大器区域之间的交叉区域。 子放大器设置在多个交叉区域中的第一交叉区域中。 起动信号供给电路配置在多个交叉区域中的第二交叉区域中，并且基于从副放大器提供的子放大器定时信号将子放大器的起始信号（控制信号）提供给子放大器 子字驱动器区域的延伸方向。
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公开(公告)号：US08000123B2
公开(公告)日：2011-08-16
申请号：US12537639
申请日：2009-08-07
申请人： Tetsuaki Okahiro , Hiromasa Noda
发明人： Tetsuaki Okahiro , Hiromasa Noda
IPC分类号： G11C5/06
CPC分类号： G11C11/4097 , G11C11/4099 , G11C11/413
摘要： There is provided a semiconductor memory device that includes: a plurality of memory mats each including a plurality of word lines, a plurality of bit lines, a plurality of memory cells each located at an intersection between the word line and the bit line, and at least one dummy word line not having connection to a dummy cell; a plurality of sense amplifier arrays located between adjacent memory mats, the sense amplifier arrays including a plurality of sense amplifiers including a pair of input/output nodes, one of which pair is connected to the bit lines of the adjacent memory mats on one side and the other of which pair is connected to the bit lines of the adjacent memory mats on the other side, respectively; and an activating unit which, in response to activation of the word line in a memory mat selected from the memory mats, activates the dummy word line in the memory mat adjacent to the selected memory mat.
摘要翻译： 提供了一种半导体存储器件，其包括：多个存储器衬垫，每个存储器衬垫包括多个字线，多个位线，多个存储器单元，每个存储单元分别位于字线和位线之间的交点处，并且在 至少一个没有连接到虚拟单元的虚拟字线; 位于相邻存储器垫之间的多个读出放大器阵列，所述读出放大器阵列包括多个读出放大器，所述多个读出放大器包括一对输入/输出节点，其中一个输出/输出节点对在一侧连接到相邻存储器阵列的位线， 另一个对分别连接到另一侧的相邻存储器垫的位线; 以及激活单元，响应于从存储器垫选择的存储器垫中的字线的激活，激活与所选存储器垫相邻的存储器垫中的虚拟字线。
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