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公开(公告)号：US20080309383A1
公开(公告)日：2008-12-18
申请号：US12107069
申请日：2008-04-21
IPC分类号： H03L7/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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2.发明授权Microcomputer and microprocessor having flash memory operable from single external power supply 失效具有从单个外部电源可操作的闪存的微计算机和微处理器公开(公告)号：US07385869B2
公开(公告)日：2008-06-10
申请号：US11797579
申请日：2007-05-04
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C7/00
摘要： A data processing apparatus supplied a first voltage from outside, includes a CPU, a first voltage generating circuit, a second voltage generating circuit, a clock generating circuit, and, a nonvolatile memory which can be accessed by the CPU. The first voltage generating circuit generates a second voltage, a voltage level of which is lower than that of the first voltage. The clock generating circuit is supplied the second voltage from the first voltage generating circuit and generates a clock signal, and the second voltage generating circuit is supplied the second voltage from the first voltage generating circuit and the clock signal from the clock generating circuit, and generates a second voltage, a voltage level of which is higher than that of the first voltage, for supplying to the nonvolatile memory.
摘要翻译： 从外部提供第一电压的数据处理装置包括CPU，第一电压产生电路，第二电压产生电路，时钟发生电路和可被CPU访问的非易失性存储器。 第一电压产生电路产生其电压电平低于第一电压的第二电压。 时钟发生电路从第一电压产生电路提供第二电压并产生时钟信号，并且第二电压产生电路从第一电压产生电路提供第二电压和来自时钟发生电路的时钟信号，并产生 其电压电平高于第一电压的第二电压，用于提供给非易失性存储器。
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公开(公告)号：US07382681B2
公开(公告)日：2008-06-03
申请号：US11708346
申请日：2007-02-21
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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4.发明授权Microcomputer and microprocessor having flash memory operable from single external power supply 失效具有从单个外部电源可操作的闪存的微计算机和微处理器公开(公告)号：US07236419B2
公开(公告)日：2007-06-26
申请号：US11365499
申请日：2006-03-02
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C7/00
摘要： A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.
摘要翻译： 提供一种半导体处理装置，其包括非易失性存储单元，电压产生单元和第一端子。 电压产生单元产生由从半导体处理装置的外部提供的操作电压产生的第一电压，并将第一电压提供给用于在其中存储数据的非易失性存储单元。 第一端子将由电压产生单元产生的第一电压提供给半导体处理装置的外部。 通过第一端子提供到半导体处理装置外部的第一电压允许检查第一电压的电压电平并校正该电压电平。
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公开(公告)号：US20060227650A1
公开(公告)日：2006-10-12
申请号：US11446217
申请日：2006-06-05
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
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公开(公告)号：US07075469B2
公开(公告)日：2006-07-11
申请号：US11246170
申请日：2005-10-11
申请人： Naoki Yada , Yasuyuki Saito
发明人： Naoki Yada , Yasuyuki Saito
IPC分类号： H03M1/78
CPC分类号： H03M1/1023 , H03M1/46 , H03M1/682 , H03M1/765
摘要： A semiconductor integrated circuit including an A/D converter capable of converting an analog signal accepted through an external terminal into a digital signal. The A/D converter includes: a ladder-type resistor for generating a reference voltage; a set of first operational amplifiers, each accepts an output voltage of the ladder-type resistor; a set of first switches, each capable of short-circuiting an input terminal and an output terminal of corresponding one of the first operational amplifiers thereby to allow an offset correction of the corresponding first operational amplifier to be made; and a comparator circuit for comparing an output voltage of each of the first operational amplifiers with the analog signal. The A/D converter can reduce a current output from the ladder-type resistor and speed up charge and discharge of the sampling capacitor.
摘要翻译： 一种包括能够将通过外部端子接收的模拟信号转换为数字信号的A / D转换器的半导体集成电路。 A / D转换器包括：用于产生参考电压的梯形电阻器; 一组第一运算放大器，每个接收梯形电阻器的输出电压; 一组第一开关，每个能够使第一运算放大器的相应一个输入端子和输出端子短路，从而允许相应的第一运算放大器的偏移校正; 以及用于将每个第一运算放大器的输出电压与模拟信号进行比较的比较器电路。 A / D转换器可以减少梯形电阻器的电流输出，并加快采样电容器的充电和放电。
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7.发明授权公开(公告)号：US06661715B2
公开(公告)日：2003-12-09
申请号：US10160074
申请日：2002-06-04
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C1604
摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.
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8.发明授权Microcomputer and microprocessor having flash memory operable from single external power supply 有权具有从单个外部电源可操作的闪存的微计算机和微处理器公开(公告)号：US06327212B1
公开(公告)日：2001-12-04
申请号：US09694487
申请日：2000-10-24
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C700
摘要： A microcomputer incorporating a flash memory which is erased and programmed electrically in a stable manner within a relatively wide range of external power supply voltages including those for low-voltage operations. The microcomputer comprises a voltage clamp unit including a reference voltage generating circuit and a constant voltage generating circuit. In operation, the voltage clamp unit generates a voltage of a low dependency on a supply voltage and clamps the generated voltage to a voltage level which, within a tolerable range, is lower than a single supply voltage externally furnished. This prevents voltages boosted by boosting circuits operating on the clamped voltage, i.e., programming and erasure voltages, from being dependent on the externally supplied voltage.
摘要翻译： 微型计算机包括闪存，其在相对较宽的外部电源电压范围内以稳定的方式被电擦除和编程，包括用于低电压操作的外部电源电压。 该微型计算机包括一个包括一个参考电压产生电路和一个恒压发生电路的电压钳位单元。 在操作中，电压钳位单元产生对电源电压的低依赖性的电压，并将所产生的电压钳位到在可容忍范围内低于外部单个电源电压的电压电平。 这可防止由钳位电压工作的升压电路（即编程和擦除电压）由外部提供的电压而提升的电压。
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9.发明申请Microcomputer and microprocessor having flash memory operable from single external power supply 失效具有从单个外部电源可操作的闪存的微计算机和微处理器公开(公告)号：US20060164889A1
公开(公告)日：2006-07-27
申请号：US11365499
申请日：2006-03-02
申请人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
发明人： Eiichi Ishikawa , Yasuyuki Saito , Masanao Sato , Naoki Yada , Kiyoshi Matsubara
IPC分类号： G11C16/04
摘要： A semiconductor processing device is provided which includes a nonvolatile memory unit, a voltage generating unit, and a first terminal. The voltage generating unit generates a first voltage generated from an operation voltage provided from outside of the semiconductor processing device and provides the first voltage to the nonvolatile memory unit for storing data therein. The first terminal provides the first voltage generated by the voltage generating unit to outside of the semiconductor processing device. This first voltage provided to outside of the semiconductor processing device via the first terminal permits checking a voltage level of the first voltage and correcting this voltage level.
摘要翻译： 提供一种半导体处理装置，其包括非易失性存储单元，电压产生单元和第一端子。 电压产生单元产生由从半导体处理装置的外部提供的操作电压产生的第一电压，并将第一电压提供给用于在其中存储数据的非易失性存储单元。 第一端子将由电压产生单元产生的第一电压提供给半导体处理装置的外部。 通过第一端子提供到半导体处理装置外部的第一电压允许检查第一电压的电压电平并校正该电压电平。
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公开(公告)号：US07061825B2
公开(公告)日：2006-06-13
申请号：US10867013
申请日：2004-06-15
IPC分类号： G11C8/00
CPC分类号： H03L7/08 , G06F1/08 , G11C7/04 , G11C7/22 , G11C7/222 , G11C2207/2254 , H03K3/0315 , H03K5/133 , H03K5/2481 , H03K2005/00039 , H03K2005/00143 , H03L7/085
摘要： A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency of the internal clock signal to coincide with the frequency of an external clock signal. The internal clock signal is used for a synchronous operation of an internal circuit. Even if an error (undesired variation) occurs in the oscillation characteristic of the oscillator circuit due to process variations, it is possible to cause an internal clock signal frequency to coincide with an external clock signal frequency corresponding to a target frequency without the need for external attachment of a crystal oscillator and the input of an external clock signal.
摘要翻译： 半导体集成电路包括存储电路，基于存储电路中保存的控制信息产生内部时钟信号的振荡电路，以及产生控制信息的逻辑电路，该控制信息使内部时钟信号的频率与 外部时钟信号的频率。 内部时钟信号用于内部电路的同步操作。 即使由于过程变化而在振荡电路的振荡特性中出现误差（不期望的变化），也可能使内部时钟信号频率与对应于目标频率的外部时钟信号频率一致，而不需要外部 晶体振荡器的附件和外部时钟信号的输入。
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