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    Multiple VCO phase lock loop architecture
    1.
    发明授权
    Multiple VCO phase lock loop architecture 有权
    多个VCO锁相环结构

    公开(公告)号：US06670833B2

    公开(公告)日：2003-12-30

    申请号：US10052264

    申请日：2002-01-23

    申请人： Nasser A. Kurd ,  Ian Young

    发明人： Nasser A. Kurd ,  Ian Young

    IPC分类号： H03L706

    CPC分类号： H03L7/0893 ,  H03L7/0896 ,  H03L7/099 ,  Y10S331/02

    摘要： A VCO phase lock loop system may include a first voltage controlled oscillator that provides a first oscillation signal relative to a first frequency and a second voltage controlled oscillator that provide a second oscillation signal relative to a second frequency. A loop filter capacitor may be associated with both the first voltage controlled oscillator and the second voltage controlled oscillator. A selection device may enable components associated with the either one of the voltage controlled oscillators while disabling components associated with the other one of the voltage controlled oscillators.

    摘要翻译： VCO锁相环系统可以包括提供相对于第一频率的第一振荡信号的第一压控振荡器和相对于第二频率提供第二振荡信号的第二压控振荡器。 环路滤波电容器可以与第一压控振荡器和第二压控振荡器两者相关联。 选择装置可以启用与压控振荡器中的任一个相关联的组件，同时禁用与压控振荡器中的另一个相关联的组件。

    System and method for scaling power of a phase-locked loop architecture
    3.
    发明授权
    System and method for scaling power of a phase-locked loop architecture 有权
    用于缩放锁相环结构的功率的系统和方法

    公开(公告)号：US08878579B2

    公开(公告)日：2014-11-04

    申请号：US13995903

    申请日：2011-12-20

    申请人： Nasser A. Kurd ,  Vaughn J. Grossnickle

    发明人： Nasser A. Kurd ,  Vaughn J. Grossnickle

    IPC分类号： H03L7/06 ,  G06F1/32 ,  G06F1/08 ,  H03L7/08

    CPC分类号： H03L7/08 ,  G06F1/08 ,  G06F1/3296 ,  Y02D10/172

    摘要： Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

    摘要翻译： 描述了用于提供具有可缩放功率的PLL架构的装置，系统和方法。 在一个实施例中，系统包括具有电压调节器的一个或多个处理单元，用于为耦合到电压调节器的锁相环（PLL）电路产生可控地调节的电源电压。 PLL电路将参考时钟信号的相位和频率与生成的反馈时钟信号的相位和频率进行比较，并且基于该比较生成输出信号。 跟踪单元基于系统的操作频率来调节可调节的电源电压。

    SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE
    4.
    发明申请
    SYSTEM AND METHOD FOR SCALING POWER OF A PHASE-LOCKED LOOP ARCHITECTURE 有权
    用于定位相位锁定环路功率的系统和方法

    公开(公告)号：US20140103973A1

    公开(公告)日：2014-04-17

    申请号：US13995903

    申请日：2011-12-20

    申请人： Nasser A. Kurd ,  Vaughn J. Grossnickle

    发明人： Nasser A. Kurd ,  Vaughn J. Grossnickle

    IPC分类号： H03L7/08

    CPC分类号： H03L7/08 ,  G06F1/08 ,  G06F1/3296 ,  Y02D10/172

    摘要： Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

    摘要翻译： 描述了用于提供具有可缩放功率的PLL架构的装置，系统和方法。 在一个实施例中，系统包括具有电压调节器的一个或多个处理单元，用于为耦合到电压调节器的锁相环（PLL）电路产生可控地调节的电源电压。 PLL电路将参考时钟信号的相位和频率与生成的反馈时钟信号的相位和频率进行比较，并且基于该比较生成输出信号。 跟踪单元基于系统的操作频率来调节可调节的电源电压。

    Glitch protection and detection for strobed data
    7.
    发明授权
    Glitch protection and detection for strobed data 有权
    毛刺保护和检测选通数据

    公开(公告)号：US06505262B1

    公开(公告)日：2003-01-07

    申请号：US09449627

    申请日：1999-11-30

    申请人： Nasser A. Kurd ,  Robert J. Greiner

    发明人： Nasser A. Kurd ,  Robert J. Greiner

    IPC分类号： H03K522

    CPC分类号： H03K5/1252 ,  G06F13/4077

    摘要： In a processing system, a glitch protection circuit receives a strobe signal and a data receiver captures a data signal in response to an output from the glitch protection circuit. Several embodiments are disclosed. In a first embodiment, a glitch protection circuit generates an output that represents a logical multiplication of a strobe signal with a delayed version of itself. In another embodiment, a pair of glitch protection circuits each sense a strobe transition and become dormant until its partner senses a strobe transition. The pair operates in a toggling fashion.

    摘要翻译： 在处理系统中，毛刺保护电路接收选通信号，并且数据接收器响应于来自毛刺保护电路的输出而捕获数据信号。 公开了几个实施例。 在第一实施例中，毛刺保护电路产生表示选通信号与其自身的延迟版本的逻辑乘法的输出。 在另一个实施例中，一对毛刺保护电路各自感知选通转换并变为休眠状态，直到其伴侣感测到频闪转换。 这对以切换的方式运作。

    High frequency system with duty cycle buffer
    8.
    发明授权
    High frequency system with duty cycle buffer 有权
    高频系统带占空比缓冲器

    公开(公告)号：US06489821B1

    公开(公告)日：2002-12-03

    申请号：US09939763

    申请日：2001-08-28

    申请人： Nasser A. Kurd ,  Jed Griffin

    发明人： Nasser A. Kurd ,  Jed Griffin

    IPC分类号： H03B100

    CPC分类号： H03L7/18 ,  G06F1/10 ,  H03L7/0891 ,  H03L7/099

    摘要： A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.

    摘要翻译： 在高频系统中设置同步装置。 同步装置包括环路控制电路，耦合到环路控制电路的压控振荡器，耦合到压控振荡器的匹配电流放大器和连接到匹配电路放大器的占空比控制缓冲器。

    Clock enable generation, synchronization, and distribution
    9.
    发明授权
    Clock enable generation, synchronization, and distribution 有权
    时钟使能生成，同步和分发

    公开(公告)号：US06266779B1

    公开(公告)日：2001-07-24

    申请号：US09169278

    申请日：1998-10-08

    申请人： Nasser A. Kurd

    发明人： Nasser A. Kurd

    IPC分类号： G06F104

    CPC分类号： G06F1/04 ,  G06F1/06

    摘要： According to one embodiment, a clock enable generator circuit comprises a decode module configured to generate enable pulses. The decode module generates the enable pulses in response to receiving a clock ratio signal. The clock enable generator circuit further includes a first and second output circuit. The first output circuit is coupled to the decode module and is configured to generate a first set of clock enables in response to receiving an enable pulse from the decode module. The second output circuit is coupled to the decode module and is configured to generate a second set of clock enables. The clock enable generator circuit is configured to generate different sets of clock enables for each of a plurality of clock ratio signals. According to a further embodiment, The clock enable generator circuit further comprises a third output circuit coupled to the decode module. The first output circuit generates the first set of clock enables in response to the decode module receiving an even ratio signal. In addition, the first and third output circuits generate the first set of clock enables in response to the decode module receiving an odd ratio signal.

    摘要翻译： 根据一个实施例，时钟使能发生器电路包括被配置为产生使能脉冲的解码模块。 解码模块响应于接收到时钟比信号而产生使能脉冲。 时钟使能发生器电路还包括第一和第二输出电路。 第一输出电路耦合到解码模块，并且被配置为响应于从解码模块接收使能脉冲而产生第一组时钟使能。 第二输出电路耦合到解码模块，并被配置为产生第二组时钟使能。 时钟使能发生器电路被配置为为多个时钟比信号中的每一个生成不同的时钟使能组。 根据另一实施例，时钟使能发生器电路还包括耦合到解码模块的第三输出电路。 第一输出电路响应于解码模块接收到偶数比信号而产生第一组时钟使能。 此外，第一和第三输出电路响应于解码模块接收奇数比信号而产生第一组时钟使能。

    VOLTAGE DROOP DETECTION AND FREQUENCY RECOVERY
    10.
    发明公开
    VOLTAGE DROOP DETECTION AND FREQUENCY RECOVERY 审中-公开

    公开(公告)号：US20230314488A1

    公开(公告)日：2023-10-05

    申请号：US17708964

    申请日：2022-03-30

    申请人： Praveen Mosalikanti ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

    发明人： Praveen Mosalikanti ,  Vaughn J. Grossnickle ,  Nasser A. Kurd

    IPC分类号： G01R19/165 ,  H03K5/00 ,  H03K5/24

    CPC分类号： G01R19/16538 ,  H03K5/00006 ,  H03K5/24

    摘要： A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.