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公开(公告)号：US08248124B2
公开(公告)日：2012-08-21
申请号：US12793533
申请日：2010-06-03
IPC分类号： H03L7/06
CPC分类号： G06F1/324 , G06F1/3296 , H03L7/0802 , H03L7/0812 , H03L7/10 , H03L7/143 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.
摘要翻译： 提出了一种低功耗延迟锁定环（DLL）。 在一个实施例中，DLL包括相位检测器，其包括参考输入和用于确定相位差的反馈输入。 DLL还包括控制器，用于确定是否向参考输入和反馈输入提供信号，使得参考输入和反馈输入例如在低功率操作期间接收相同的输入。
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公开(公告)号：US20110298501A1
公开(公告)日：2011-12-08
申请号：US12793533
申请日：2010-06-03
CPC分类号： G06F1/324 , G06F1/3296 , H03L7/0802 , H03L7/0812 , H03L7/10 , H03L7/143 , Y02D10/126 , Y02D10/172 , Y02D50/20
摘要： A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.
摘要翻译： 提出了一种低功耗延迟锁定环（DLL）。 在一个实施例中，DLL包括相位检测器，其包括参考输入和用于确定相位差的反馈输入。 DLL还包括控制器，用于确定是否向参考输入和反馈输入提供信号，使得参考输入和反馈输入例如在低功率操作期间接收相同的输入。
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公开(公告)号：US20230314488A1
公开(公告)日：2023-10-05
申请号：US17708964
申请日：2022-03-30
IPC分类号： G01R19/165 , H03K5/00 , H03K5/24
CPC分类号： G01R19/16538 , H03K5/00006 , H03K5/24
摘要： A single droop detector and an asynchronous frequency recovery circuit may be used to slow down a frequency asynchronously when a voltage droop is detected and exit the droop event synchronously by gradually changing an electronic oscillator buffer capacitance until the frequency has been fully restored. This combination of a single droop detector and an asynchronous frequency recovery circuit may provide reduced detection and response latency. This solution may also provide improved performance in the presence of multiple voltage droop events that occur before a frequency has been fully restored from the previous droop. This solution also reduces or eliminates frequency overshoots and secondary voltage droops.
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公开(公告)号：US20120019285A1
公开(公告)日：2012-01-26
申请号：US12840691
申请日：2010-07-21
IPC分类号： H03K3/01
CPC分类号： H03K17/22 , H03K19/0008
摘要： Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
摘要翻译： 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。
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公开(公告)号：US08350610B2
公开(公告)日：2013-01-08
申请号：US12840691
申请日：2010-07-21
IPC分类号： H03K3/02
CPC分类号： H03K17/22 , H03K19/0008
摘要： Described herein is a method and apparatus to wake-up analog bias signals with minimum delay. The apparatus comprises a first logic unit operable to adjust a signal level of a gated bias signal via a first predetermined signal in response to a power-down event; a comparator operable to compare the gated bias signal with an un-gated bias signal, and operable to generate an output signal indicating the comparison result; and a self-timed logic unit coupled to the comparator and operable to generate a wake-up signal in response to an end of the power-down event and the output signal.
摘要翻译： 这里描述了以最小延迟来唤醒模拟偏置信号的方法和装置。 该装置包括第一逻辑单元，用于响应于断电事件经由第一预定信号调节门控偏置信号的信号电平; 比较器，用于将门控偏置信号与非门控偏置信号进行比较，并且可操作以产生指示比较结果的输出信号; 以及耦合到所述比较器的自定时逻辑单元，用于响应于所述断电事件和所述输出信号的结束而产生唤醒信号。
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6.发明申请METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS 有权用于确定模拟电路内部和模拟电路变化的方法和装置公开(公告)号：US20110285469A1
公开(公告)日：2011-11-24
申请号：US13197525
申请日：2011-08-03
IPC分类号： H03K3/03
CPC分类号： G01R31/2894 , H03K3/0315
摘要： Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
摘要翻译： 这里描述了用于确定与一个或多个模拟装置耦合的振荡器的频率的方法和装置，并且用于确定与一个或多个模拟装置相关联的模拟特性中的管芯内或片内变化，基于 振荡器频率。 模拟特性包括输出信号摆幅，带宽，偏移，增益和延迟线的线性度和范围。 一个或多个模拟设备包括输入输出（I / O）缓冲器，模拟放大器和延迟线。 该方法还包括基于对模拟特性的管芯内和/或跨模变化的确定来更新模拟模型文件。
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7.发明授权Method and apparatus for determining within-die and across-die variation of analog circuits 有权用于确定模拟电路的管芯内和模具间变化的方法和装置公开(公告)号：US08031017B2
公开(公告)日：2011-10-04
申请号：US12492940
申请日：2009-06-26
CPC分类号： G01R31/2894 , H03K3/0315
摘要： Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
摘要翻译： 这里描述了用于确定与一个或多个模拟装置耦合的振荡器的频率的方法和装置，并且用于确定与一个或多个模拟装置相关联的模拟特性中的管芯内或片内变化，基于 振荡器频率。 模拟特性包括输出信号摆幅，带宽，偏移，增益和延迟线的线性度和范围。 一个或多个模拟设备包括输入输出（I / O）缓冲器，模拟放大器和延迟线。 该方法还包括基于对模拟特性的管芯内和/或跨模变化的确定来更新模拟模型文件。
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8.发明授权Method and apparatus for determining within-die and across-die variation of analog circuits 有权用于确定模拟电路的管芯内和模具间变化的方法和装置公开(公告)号：US08502612B2
公开(公告)日：2013-08-06
申请号：US13197525
申请日：2011-08-03
CPC分类号： G01R31/2894 , H03K3/0315
摘要： Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
摘要翻译： 这里描述了用于确定与一个或多个模拟装置耦合的振荡器的频率的方法和装置，并且用于确定与一个或多个模拟装置相关联的模拟特性中的管芯内或片内变化，基于 振荡器频率。 模拟特性包括输出信号摆幅，带宽，偏移，增益和延迟线的线性度和范围。 一个或多个模拟设备包括输入输出（I / O）缓冲器，模拟放大器和延迟线。 该方法还包括基于对模拟特性的管芯内和/或跨模变化的确定来更新模拟模型文件。
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9.发明申请METHOD AND APPARATUS FOR DETERMINING WITHIN-DIE AND ACROSS-DIE VARIATION OF ANALOG CIRCUITS 有权用于确定模拟电路内部和模拟电路变化的方法和装置公开(公告)号：US20100327936A1
公开(公告)日：2010-12-30
申请号：US12492940
申请日：2009-06-26
CPC分类号： G01R31/2894 , H03K3/0315
摘要： Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die or across-die variations in an analog property associated with the one or more analog devices, the determining based on the oscillator frequency. The analog property includes output signal swing, bandwidth, offset, gain, and delay line linearity and range. The one or more analog devices include input-output (I/O) buffer, analog amplifier, and delay line. The method further comprises updating a simulation model file based on the determining of the within-die and/or across-die variations of the analog property.
摘要翻译： 这里描述了用于确定与一个或多个模拟装置耦合的振荡器的频率的方法和装置，并且用于确定与一个或多个模拟装置相关联的模拟特性中的管芯内或片内变化，基于 振荡器频率。 模拟特性包括输出信号摆幅，带宽，偏移，增益和延迟线的线性度和范围。 一个或多个模拟设备包括输入输出（I / O）缓冲器，模拟放大器和延迟线。 该方法还包括基于对模拟特性的管芯内和/或跨模变化的确定来更新模拟模型文件。
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公开(公告)号：US20110148486A1
公开(公告)日：2011-06-23
申请号：US12640842
申请日：2009-12-17
申请人： Praveen Mosalikanti , Nasser Kurd
发明人： Praveen Mosalikanti , Nasser Kurd
CPC分类号： H03L7/0805 , H03K5/133 , H03K5/15 , H03K2005/00032 , H03K2005/00104 , H03L7/0812 , H03L7/0816
摘要： Methods and systems to generate multiple phases of a clock may include a delay locked loop (DLL) to generate a bias signal to control a delay time through DLL delay elements in response to a first clock, and a plurality of a quadrature slave delay lines (SDLs), each to generate a plurality of successively phase shifted clocks over a quadrant of a corresponding selected phase of a second clock. The SDLs may be biased with the DLL bias signal to control phase differences between the generated clocks. One or more phase interpolators, such as contention based phase interpolators, may be coupled to outputs of each SDL. A frequency of the second clock may be equal to or greater than a frequency of the first clock. The SDLs may be implemented with fewer delay elements than the DLL.
摘要翻译： 用于产生时钟的多个相位的方法和系统可以包括延迟锁定环（DLL），以产生偏置信号，以响应于第一时钟来控制通过DLL延迟元件的延迟时间，以及多个正交从属延迟线 SDL），其每一个在第二时钟的相应选择的相位的象限上产生多个连续相移的时钟。 SDL可以用DLL偏置信号偏置来控制所产生的时钟之间的相位差。 一个或多个相位内插器，例如基于竞争的相位内插器，可以耦合到每个SDL的输出。 第二时钟的频率可以等于或大于第一时钟的频率。 SDL可以用比DLL更少的延迟元件来实现。
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