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    Non-Continuous encapsulation layer for MIM capacitor
    5.
    发明授权
    Non-Continuous encapsulation layer for MIM capacitor 失效
    MIM电容器的非连续封装层

    公开(公告)号：US06913965B2

    公开(公告)日：2005-07-05

    申请号：US10709133

    申请日：2004-04-15

    申请人： Wagdi W. Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    发明人： Wagdi W. Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    IPC分类号： H01L21/02 ,  H01L21/8242

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION
    6.
    发明申请
    METAL-INSULATOR-METAL CAPACITOR AND METHOD OF FABRICATION 有权
    金属绝缘体 - 金属电容器和制造方法

    公开(公告)号：US20050067701A1

    公开(公告)日：2005-03-31

    申请号：US10605444

    申请日：2003-09-30

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/52 ,  H01L21/44

    CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的上表面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。

    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme
    7.
    发明授权
    Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme 失效
    制造更高性能的电容密度MIMcap的廉价方法可以集成到铜互连方案中

    公开(公告)号：US07687867B2

    公开(公告)日：2010-03-30

    申请号：US11846248

    申请日：2007-08-28

    申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Zhong-Xiang He ,  William J. Murphy ,  Vidhya Ramachandran

    IPC分类号： H01L29/72

    CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    摘要翻译： 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

    Non-continuous encapsulation layer for MIM capacitor
    8.
    发明授权
    Non-continuous encapsulation layer for MIM capacitor 有权
    MIM电容器的非连续封装层

    公开(公告)号：US07326987B2

    公开(公告)日：2008-02-05

    申请号：US10908491

    申请日：2005-05-13

    申请人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    发明人： Wagdi Abadeer ,  Eric Adler ,  Zhong-Xiang He ,  Bradley Orner ,  Vidhya Ramachandran ,  Barbara A. Waterhouse ,  Michael Zierak

    IPC分类号： H01L27/108

    CPC分类号： H01L28/57

    摘要： The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

    摘要翻译： 本发明涉及形成在半导体衬底上的金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）。 FET形成在线路前端（FEOL）电平以下的MIM电容器下面，这些电容器形成在上部后端（BEOL）电平。 选择性地形成绝缘体层以封装MIM电容器的至少顶板，以保护MIM电容器免受由于诸如反应离子蚀刻等工艺步骤的损害。 通过在MIM电容器上选择性地形成绝缘体层，提供层间电介质层中的开口，使得可以发生氢和/或氘到FET的扩散。

    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME
    9.
    发明申请
    INEXPENSIVE METHOD OF FABRICATING A HIGHER PERFORMANCE CAPACITANCE DENSITY MIMCAP INTEGRABLE INTO A COPPER INTERCONNECT SCHEME 失效
    将高性能电容密度MIMCAP合并成一个铜互连方案的独立方法

    公开(公告)号：US20070290359A1

    公开(公告)日：2007-12-20

    申请号：US11846248

    申请日：2007-08-28

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Zhong-Xiang He ,  William Murphy ,  Vidhya Ramachandran

    IPC分类号： H01L23/48

    CPC分类号： H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method to integrate MIM capacitors into conductive interconnect levels, with low cost impact, and high yield, reliability and performance than existing integration methods is provided. This is accomplished by recessing a prior level dielectric for MIM capacitor level alignment followed by deposition and patterning of the MIM capacitor films. Specifically, the method includes providing a substrate including a wiring level, the wiring level comprising at least one conductive interconnect formed in a dielectric layer; selectively removing a portion of the dielectric layer to recess the dielectric layer below an upper surface of the at least one conductive interconnect; forming a dielectric stack upon the at least one conductive interconnect and the recessed dielectric layer; and forming a metal-insulator-metal (MIM) capacitor on the dielectric stack. The MIM capacitor includes a bottom plate electrode, a dielectric and a top plate electrode. The bottom and top plate electrodes can comprise the same or different conductive metal.

    摘要翻译： 提供了一种将MIM电容器集成到导电互连级别中的方法，具有低成本影响，并且提供了比现有集成方法高的产量，可靠性和性能。 这通过将用于MIM电容器电平对准的先前级别的电介质凹入，然后MIM电容器膜的沉积和图案化来实现。 具体地，该方法包括提供包括布线层的衬底，所述布线层包括形成在电介质层中的至少一个导电布线; 选择性地去除所述电介质层的一部分以使所述电介质层在所述至少一个导电互连的上表面下方凹陷; 在所述至少一个导电互连和所述凹入的介电层上形成电介质叠层; 以及在介电叠层上形成金属绝缘体金属（MIM）电容器。 MIM电容器包括底板电极，电介质和顶板电极。 底板和顶板电极可以包括相同或不同的导电金属。

    Metal-insulator-metal capacitor and method of fabrication
    10.
    发明申请
    Metal-insulator-metal capacitor and method of fabrication 审中-公开
    金属绝缘体金属电容器及其制造方法

    公开(公告)号：US20050156278A1

    公开(公告)日：2005-07-21

    申请号：US11028425

    申请日：2005-01-03

    申请人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    发明人： Douglas Coolbaugh ,  Ebenezer Eshun ,  Jeffrey Gambino ,  Zhong-Xiang He ,  Vidhya Ramachandran

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/48 ,  H01L29/00

    CPC分类号： H01L21/7687 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for a MIM capacitor, the structure including: an electronic device, comprising: an interlevel dielectric layer formed on a semiconductor substrate; a copper bottom electrode formed in the interlevel dielectric layer, a top surface of the bottom electrode co-planer with a top surface of the interlevel dielectric layer; a conductive diffusion barrier in direct contact with the top surface of the bottom electrode; a MIM dielectric in direct contact with a top surface of the conductive diffusion barrier; and a top electrode in direct contact with a top surface of the MIM dielectric. The conductive diffusion barrier may be recessed into the copper bottom electrode or an additional recessed conductive diffusion barrier provided. Compatible resistor and alignment mark structures are also disclosed.

    摘要翻译： 一种MIM电容器的方法和结构，该结构包括：电子器件，包括：形成在半导体衬底上的层间电介质层; 形成在所述层间电介质层中的铜底电极，所述底电极共平面的顶面与所述层间电介质层的顶面形成; 与底部电极的顶表面直接接触的导电扩散阻挡层; 与所述导电扩散阻挡层的顶表面直接接触的MIM电介质; 以及与MIM电介质的顶表面直接接触的顶部电极。 导电扩散阻挡层可以凹进到铜底电极或设置的另外的凹入的导电扩散阻挡层中。 还公开了兼容的电阻器和对准标记结构。