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公开(公告)号：US20100321842A1
公开(公告)日：2010-12-23
申请号：US12489774
申请日：2009-06-23
IPC分类号： H02H9/00 , H01L21/3205
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.
摘要翻译： 提供了具有与通过晶片通孔结构和制造方法的连接的静电放电（ESD）结构。 该结构包括与通过晶片通孔串联电连接的静电放电（ESD）网络。 更具体地，ESD电路包括位于接合焊盘下方的接合焊盘和ESD网络。 ESD电路还包括直接与ESD网络串联电连接并且还电连接到VSS的直通晶片通孔结构。
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公开(公告)号：US08530319B2
公开(公告)日：2013-09-10
申请号：US12904435
申请日：2010-10-14
申请人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
发明人： Ephrem G. Gebreselasie , Joseph M. Lukaitis , Robert R. Robison , William R. Tonti , Ping-Chuan Wang
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and a method of manufacturing an e-fuse includes a substrate, a patterned gate insulator on the substrate, and a patterned gate conductor on the patterned gate insulator. The patterned gate conductor has sidewalls and a top. A silicide contacts the sidewalls of the patterned gate conductor, the top of the patterned gate conductor, and a region of the substrate adjacent the patterned gate insulator and the patterned gate conductor.
摘要翻译： 一种制造电熔丝的装置和方法包括：衬底，衬底上的图案化栅极绝缘体，以及图案化栅极绝缘体上的图案化栅极导体。 图案化的栅极导体具有侧壁和顶部。 硅化物接触图案化栅极导体的侧壁，图案化栅极导体的顶部以及与图案化栅极绝缘体和图案化栅极导体相邻的衬底的区域。
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公开(公告)号：US08054597B2
公开(公告)日：2011-11-08
申请号：US12489774
申请日：2009-06-23
IPC分类号： H02H3/22
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： Electrostatic discharge (ESD) structures having a connection to a through wafer via structure and methods of manufacture are provided. The structure includes an electrostatic discharge (ESD) network electrically connected in series to a through wafer via. More specifically, the ESD circuit includes a bond pad and an ESD network located under the bond pad. The ESD circuit further includes a through wafer via structure electrically connected in series directly to the ESD network, and which is also electrically connected to VSS.
摘要翻译： 提供了具有与通过晶片通孔结构和制造方法的连接的静电放电（ESD）结构。 该结构包括与通过晶片通孔串联电连接的静电放电（ESD）网络。 更具体地，ESD电路包括位于接合焊盘下方的接合焊盘和ESD网络。 ESD电路还包括直接与ESD网络串联电连接并且还电连接到VSS的直通晶片通孔结构。
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公开(公告)号：US07876547B2
公开(公告)日：2011-01-25
申请号：US11755502
申请日：2007-05-30
摘要： Vertical parallel plate (VPP) capacitor structures that utilize different spacings between conductive plates in different levels of the capacitor stack. The non-even spacings of the conductive plates in the capacitor stack decrease the susceptibility of the capacitor stack of the VPP capacitor to ESD-promoted failures. The non-even spacings may be material specific in that, for example, the spacings between adjacent conductive plates in different levels of the capacitor stack may be chosen based upon material failure mechanisms for plates containing different materials.
摘要翻译： 垂直平行板（VPP）电容器结构，其在电容器堆叠的不同级别的导电板之间利用不同的间隔。 电容器堆叠中的导电板的非均匀间距降低了VPP电容器的电容器堆叠对ESD促进故障的敏感性。 非均匀间距可以是材料特定的，例如，可以基于包含不同材料的板的材料破坏机制来选择电容器堆叠的不同级别中的相邻导电板之间的间隔。
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5.发明授权Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor 有权金属栅极集成结构和方法，包括金属保险丝，反熔丝和/或电阻公开(公告)号：US08159040B2
公开(公告)日：2012-04-17
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。
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6.发明授权Product and method for integration of deep trench mesh and structures under a bond pad 有权深沟槽网格和结合垫下结构的整合的产品和方法公开(公告)号：US08044510B2
公开(公告)日：2011-10-25
申请号：US12256089
申请日：2008-10-22
IPC分类号： H01L23/48
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/823481 , H01L21/8249 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.
摘要翻译： 一种结构包括基底。 沟槽结构布置在衬底内。 将薄膜放置在层间介质垫之下和沟槽结构的部分之间。
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7.发明申请PRODUCT AND METHOD FOR INTEGRATION OF DEEP TRENCH MESH AND STRUCTURES UNDER A BOND PAD 有权产品和方法，用于整合深层沥青网和结构桩公开(公告)号：US20090127628A1
公开(公告)日：2009-05-21
申请号：US12256089
申请日：2008-10-22
IPC分类号： H01L29/78 , H01L27/088
CPC分类号： H01L27/0207 , H01L21/76224 , H01L21/823481 , H01L21/8249 , H01L27/08 , H01L2924/0002 , H01L2924/00
摘要： A structure includes a substrate. A trench structure is arranged within the substrate. A film is placed under an interlevel dielectric pad and between portions of the trench structure.
摘要翻译： 一种结构包括基底。 沟槽结构布置在衬底内。 将薄膜放置在层间介质垫之下和沟槽结构的部分之间。
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公开(公告)号：US08586423B2
公开(公告)日：2013-11-19
申请号：US13168232
申请日：2011-06-24
申请人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
发明人： Renata Camillo-Castillo , Erik M. Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Yun Shi , Andreas Stricker
IPC分类号： H01L21/02
CPC分类号： H01L29/7315 , G06F17/5063 , H01L27/0262 , H01L29/66393 , H01L29/7436
摘要： Device structures, fabrication methods, operating methods, and design structures for a silicon controlled rectifier. The method includes applying a mechanical stress to a region of a silicon controlled rectifier (SCR) at a level sufficient to modulate a trigger current of the SCR. The device and design structures include a SCR with an anode, a cathode, a first region, and a second region of opposite conductivity type to the first region. The first and second regions of the SCR are disposed in a current-carrying path between the anode and cathode of the SCR. A layer is positioned on a top surface of a semiconductor substrate relative to the first region and configured to cause a mechanical stress in the first region of the SCR at a level sufficient to modulate a trigger current of the SCR.
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9.发明申请公开(公告)号：US20090102016A1
公开(公告)日：2009-04-23
申请号：US11876402
申请日：2007-10-22
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L23/53223 , H01L23/53238 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a vertical parallel plate capacitor structure with a first plurality of conductive plates and a second plurality of conductive plates having an overlying relationship with the first plurality of conductive plates. The first plurality of conductive plates are spaced apart by a first distance. The second plurality of conductive plates are spaced apart by a second distance different than the first distance
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括具有第一多个导电板的垂直平行板电容器结构和与第一多个导电板具有重叠关系的第二多个导电板。 第一多个导电板间隔第一距离。 所述第二多个导电板间隔开与第一距离不同的第二距离
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10.发明授权公开(公告)号：US08598660B2
公开(公告)日：2013-12-03
申请号：US13150612
申请日：2011-06-01
申请人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
发明人： Renata Camillo-Castillo , Erik Mattias Dahlstrom , Robert J. Gauthier, Jr. , Ephrem G. Gebreselasie , Richard A. Phelps , Jed Hickory Rankin , Yun Shi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L29/0653 , H01L29/1045 , H01L29/66659 , H01L29/66689 , H01L29/7816 , H01L29/7835 , H01L29/7843
摘要： A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.
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