公开(公告)号：US08159040B2

公开(公告)日：2012-04-17

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L29/00

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：US20090283840A1

公开(公告)日：2009-11-19

申请号：US12119526

申请日：2008-05-13

申请人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

发明人： Douglas D. Coolbaugh ,  Ebenezer E. Eshun ,  Ephrem G. Gebreselasie ,  Zhong-Xiang He ,  Herbert Lei Ho ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Robert Mark Rassel ,  John Matthew Safran ,  Kenneth Jay Stein ,  Norman Whitelaw Robson ,  Ping-Chuan Wang ,  Hongwen Yan

IPC分类号： H01L27/06 ,  H01L21/8234

CPC分类号： H01L27/0629 ,  H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.

摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。

公开(公告)号：US08004060B2

公开(公告)日：2011-08-23

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US20090141533A1

公开(公告)日：2009-06-04

申请号：US11946938

申请日：2007-11-29

申请人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

发明人： Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Dan Moy ,  Norman W. Robson ,  John M. Safran ,  Kenneth J. Stein

IPC分类号： G11C17/08 ,  H01L27/20 ,  H01L21/768

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.

摘要翻译： 金属层和半导体层顺序地沉积在基板上。 半导体层和金属层被光刻图案化以形成半导体部分和金属栅极部分的堆叠，其优选地与至少一个金属栅极叠层的形成同时进行。 在一个实施例中，半导体部分的尺寸减小，并且金属半导体合金部分通过金属化形成在半导体部分上。 在由此形成的第一电反熔丝中，金属半导体合金部分可以电铸以在金属半导体合金部分和金属栅极部分之间形成短路。 在另一个实施例中，在半导体部分上形成两个非接合的金属半导体合金部分。 在由此形成的第二电反熔丝中，金属半导体合金部分可以被电铸以在两个先前接合的金属半导体合金部分之间形成短路。

公开(公告)号：US20090040006A1

公开(公告)日：2009-02-12

申请号：US11835846

申请日：2007-08-08

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01H85/143 ,  B23P19/00

CPC分类号： G11C17/16 ,  Y10T29/49117

摘要： A layer of semiconductor material is patterned to form a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. A first metal layer is deposited on the patterned semiconductor material layer. A dielectric material layer is deposited and lithographically patterned to cover a middle portion of the fuselink, followed by a deposition of a second metal layer. A thin metal semiconductor alloy is formed in the middle of the fuselink and thick metal semiconductor alloy alloys are formed abutting the thin metal semiconductor alloy alloy. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink. The divergence of electrical current is enhanced at the interfaces due to a sudden change of a cross-sectional area available for current conduction.

摘要翻译： 图案化半导体材料层以形成阴极半导体部分，熔丝半导体部分和阳极半导体部分。 在图案化的半导体材料层上沉积第一金属层。 介电材料层被沉积并且被光刻图案化以覆盖该熔丝的中间部分，随后沉积第二金属层。 在熔体中间形成有薄金属半导体合金，并且与金属半导体合金合金形成邻接的厚金属半导体合金合金。 所产生的本发明的电熔丝具有界面，在该界面处，较薄的金属半导体合金与所述熔丝中的较厚的金属半导体合金相邻。 由于可用于电流传导的横截面积的突然变化，在接口处的电流的发散度增强。

公开(公告)号：US08163640B2

公开(公告)日：2012-04-24

申请号：US11874385

申请日：2007-10-18

申请人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Xiangdong Chen ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L27/06 ,  H01L21/3205

CPC分类号： H01L27/0617 ,  H01L23/5256 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.

摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。

公开(公告)号：US20100181643A1

公开(公告)日：2010-07-22

申请号：US12354996

申请日：2009-01-16

申请人： Chandrasekharan Kothandaraman ,  Deok-kee Kim ,  Dureseti Chidambarrao ,  William K. Henson

发明人： Chandrasekharan Kothandaraman ,  Deok-kee Kim ,  Dureseti Chidambarrao ,  William K. Henson

IPC分类号： H01L23/525

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.

摘要翻译： 熔丝包括熔丝链接区域，第一区域和第二区域。 熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。

公开(公告)号：US07550323B2

公开(公告)日：2009-06-23

申请号：US11835800

申请日：2007-08-08

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.

摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。

公开(公告)号：US20090096059A1

公开(公告)日：2009-04-16

申请号：US11870007

申请日：2007-10-10

申请人： Anil Kumar Chinthakindi ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

发明人： Anil Kumar Chinthakindi ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman ,  Byeongju Park

IPC分类号： H01L29/00 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.

摘要翻译： 熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。 至少部分单晶半导体材料层通过间隙与衬底分离。 单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。

公开(公告)号：US20090042341A1

公开(公告)日：2009-02-12

申请号：US11835800

申请日：2007-08-08

申请人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

发明人： Dureseti Chidambarrao ,  William K. Henson ,  Deok-kee Kim ,  Chandrasekharan Kothandaraman

IPC分类号： H01L21/82

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.

摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。