公开(公告)号：US5991880A

公开(公告)日：1999-11-23

申请号：US190053

申请日：1998-11-10

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

摘要翻译： 用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。 在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。 如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。 在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

公开(公告)号：US5841867A

公开(公告)日：1998-11-24

申请号：US742711

申请日：1996-11-01

申请人： Neil G. Jacobson ,  Derek R. Curd

发明人： Neil G. Jacobson ,  Derek R. Curd

IPC分类号： G01R31/3185 ,  H04L9/00

CPC分类号： G01R31/318547 ,  G01R31/318516

摘要： The present invention provides an efficient programming verification system for Programmable Logic Devices (PLDs). Based upon IEEE JTAG standard boundary scan test architecture, the invention provides a novel test architecture including a configuration register and a signature analyzer coupled between the TDI and TDO pins of the JTAG architecture. The configuration register of the invention comprises three parts: an address register/counter, a data register, a status register. The address register/counter performs dual functions depending upon an instruction received by an instruction register. The invention eliminates the need to load each address sequentially into the address register/counter for programming by enabling the address register/counter to auto-increment the address for memory locations. After loading an initial address value, the address register/counter automatically increments the address for programming memory cells. To verify PLD programming, the invention applies a signature analyzer coupled between the TDI and TDO pins. A single input linear feedback shift register (SISR) or multiple LFSR (MISR) can be used to implement a signature analyzer in accordance with the invention. SISR or MISR uses a characteristic polynomial to generate a near-unique signature checksum for an input sequence. The accumulated signature checksum is then provided serially through the TDO pin for inspection.

摘要翻译： 本发明提供了一种用于可编程逻辑器件（PLD）的高效编程验证系统。 基于IEEE JTAG标准边界扫描测试架构，本发明提供了一种新颖的测试架构，包括配置寄存器和耦合在JTAG架构的TDI和TDO引脚之间的签名分析器。 本发明的配置寄存器包括三个部分：地址寄存器/计数器，数据寄存器，状态寄存器。 地址寄存器/计数器根据指令寄存器接收的指令执行双重功能。 本发明消除了通过使地址寄存器/计数器自动增加存储器位置的地址而将每个地址顺序地加载到地址寄存器/计数器中以进行编程的需要。 加载初始地址值后，地址寄存器/计数器自动递增编程存储单元的地址。 为了验证PLD编程，本发明应用了耦合在TDI和TDO引脚之间的签名分析器。 可以使用单输入线性反馈移位寄存器（SISR）或多个LFSR（MISR）来实现根据本发明的签名分析器。 SISR或MISR使用特征多项式来为输入序列生成近似唯一的签名校验和。 累积签名校验和然后通过TDO引脚提供串行检查。

公开(公告)号：US06314539B1

公开(公告)日：2001-11-06

申请号：US09176659

申请日：1998-10-21

申请人： Neil G. Jacobson ,  Derek R. Curd

发明人： Neil G. Jacobson ,  Derek R. Curd

IPC分类号： G01R3128

CPC分类号： G01R31/318541

摘要： A Boundary-Scan register (BSR) cell including a bypass circuit for selectively routing data signals around the data shift register of the BSR cell so that the BSR cell can be effectively removed from a BSR chain during Boundary-Scan Test procedures involving IEEE Standard 1149.1 compliant integrated circuits. In one embodiment, the BSR cell includes a bypass MUX having a first input terminal connected to a test data input (TDI) terminal of the BSR cell, a second input terminal connected to an output terminal of the shift register, and an output terminal connected to the test data output (TDO) terminal. The BSR cell operates in a “normal” mode (i.e., included in the BSR chain) when the bypass MUX is controlled to pass data signals output from the shift register to the TDO terminal. In contrast, the BSR cell is selectively bypassed (i.e., removed from the BSR chain) when the bypass MUX is controlled to pass the TDI signal to the TDO terminal. The BSR cell also includes mode control MUX having a first input terminal connected to receive a MODE signal generated by a Boundary-Scan TAP controller, a second input terminal connected to an OFF (disable) signal source, and an output terminal connected to the output MUX of the BSR cell. When the BSR cell operates in the “normal”, the mode control MUX is controlled to pass the MODE signal to the output MUX. In contrast, when the BSR cell is selectively bypassed, the OFF signal is passed to the output MUX.

摘要翻译： 一种边界扫描寄存器（BSR）单元，包括用于选择性地在BSR单元的数据移位寄存器周围数据信号路由的旁路电路，使得可以在涉及IEEE标准1149.1的边界扫描测试程序期间将BSR单元有效地从BSR链中移除 兼容的集成电路。 在一个实施例中，BSR单元包括旁路MUX，其具有连接到BSR单元的测试数据输入（TDI）端的第一输入端，连接到移位寄存器的输出端的第二输入端和连接的输出端 到测试数据输出（TDO）端子。 当旁路MUX被控制以将从移位寄存器输出的数据信号传递到TDO终端时，BSR单元工作在“正常”模式（即包括在BSR链中）。 相反，当旁路MUX被控制以将TDI信号传递到TDO终端时，BSR单元被选择性地旁路（即从BSR链移除）。 BSR单元还包括模式控制MUX，其具有被连接以接收由边界扫描TAP控制器产生的MODE信号的第一输入端子，连接到OFF（禁止）信号源的第二输入端子以及连接到输出端的输出端子 BSR单元的MUX。 当BSR单元工作在“正常”时，控制模式控制MUX将MODE信号传递到输出MUX。 相反，当选择性地旁路BSR单元时，OFF信号被传递到输出MUX。

公开(公告)号：US5838901A

公开(公告)日：1998-11-17

申请号：US692389

申请日：1996-08-05

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F1/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

公开(公告)号：US07966534B1

公开(公告)日：2011-06-21

申请号：US12484150

申请日：2009-06-12

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： G01R31/28 ,  G01R31/02 ,  G06F11/00 ,  H03K19/173 ,  H03K19/177

CPC分类号： G01R31/318516 ,  G06F11/0721 ,  G06F11/0757 ,  G06F11/0793 ,  G11C2029/0411

摘要： A method of detecting an error when loading a programmable integrated circuit (IC) can include detecting a predetermined bit pattern indicating a start of a bitstream within the programmable IC, starting a timer within the programmable IC responsive to detecting the predetermined bit pattern, and determining whether a bitstream load complete condition has occurred prior to expiration of the timer. When the timer expires prior to an occurrence of the bitstream load complete condition, at least one recovery action can be implemented.

摘要翻译： 当加载可编程集成电路（IC）时检测错误的方法可以包括检测指示可编程IC内的比特流开始的预定位模式，响应于检测到预定位模式，启动可编程IC内的定时器，以及确定 在定时器到期之前是否已经发生比特流加载完成条件。 当定时器在比特流加载完成条件发生之前到期时，可以实现至少一个恢复动作。

公开(公告)号：US07913209B1

公开(公告)日：2011-03-22

申请号：US12047663

申请日：2008-03-13

申请人： Kang Wu ,  Neil G. Jacobson

发明人： Kang Wu ,  Neil G. Jacobson

IPC分类号： G06F17/50 ,  G06F7/00

CPC分类号： G06F17/5045

摘要： A cycle basis is efficiently determined for a directed graph. A first depth-first search of the directed graph classifies each of the edges of the directed graph to have a type that is one of a within-tree type for an edge within a tree of the first depth first search, a forward type for an edge skipping forward along the tree, a back type for an edge directed back along the tree, or a cross type for an edge between two subtrees of the tree. A second depth-first search of the directed graph determines a respective cycle for each of the edges of the back type. A third depth-first search of the directed graph determines a respective cycle for each of the edges of the cross type that is included a cycle. The basis is output the basis that specifies each of the respective cycles.

摘要翻译： 针对有向图有效地确定周期的基础。 有向图的第一深度优先搜索将有向图的每个边缘分类为对于第一深度第一搜索的树中的边缘的树内类型之一的类型，对于 边缘沿着树向前跳，沿着树向后指向的边的背面类型，或树的两个子树之间的边缘的交叉类型。 有向图的第二深度优先搜索确定后面类型的每个边缘的相应周期。 有向图的第三深度优先搜索确定包括循环的交叉类型的每个边缘的相应周期。 基础是输出指定各个周期的基础。

公开(公告)号：US07363545B1

公开(公告)日：2008-04-22

申请号：US10162239

申请日：2002-06-03

申请人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Jerry Mao

发明人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Jerry Mao

IPC分类号： G06F11/00 ,  G01R31/28

CPC分类号： G06F11/267

摘要： A software architecture for facilitating communications between a computer or workstation and a programming apparatus used to program a PLD by minimizing the number of two-way communications on a standard download cable (e.g., RS232, USB) connected between the computer and the programming apparatus. A first component used to encode programming instructions and configuration data to form a first transmission stream that is transmitted to the programming apparatus in a single, long burst. The programming apparatus includes a second component of the software architecture that interprets the first transmission stream and programs the PLD using, for example, Boundary-Scan signals that are generated in response to the programming instructions and configuration data. A buffer memory stores data shifted out of the PLD during the programming operation, which is transmitted to the computer in a single, long burst after the first transmission stream is completed.

摘要翻译： 一种用于促进计算机或工作站与用于通过连接在计算机和编程设备之间的标准下载电缆（例如，RS232，USB））上最小化双向通信数量来编程PLD的程序设备之间的通信的软件架构。 用于编码编程指令和配置数据以形成以单个长突发发送到编程设备的第一传输流的第一组件。 编程设备包括软件架构的第二组件，其解释第一传输流并且使用例如响应于编程指令和配置数据生成的边界扫描信号对PLD进行编程。 缓冲存储器存储在编程操作期间从PLD移出的数据，其在第一传输流完成之后以单个长的突发发送到计算机。

公开(公告)号：US5784577A

公开(公告)日：1998-07-21

申请号：US699068

申请日：1996-08-05

申请人： Neil G. Jacobson ,  David Chiang

发明人： Neil G. Jacobson ,  David Chiang

IPC分类号： G06F1/00 ,  G06F12/14 ,  G06F21/00 ,  G11C16/22 ,  G06F13/10

CPC分类号： G06F21/76 ,  G06F12/1466 ,  G11C16/22 ,  G06F2207/7219

摘要： In an automated control system, a user must be authorized to modify the configuration data of a programmable logic device (PLD). After authorization is confirmed, the PLD is unlocked. Then, the configuration data of the PLD and the contents of a version control register are read back and archived, thereby providing a security back-up should the user need to retrieve the original data. After readback, the version control number is automatically incremented. This incremented version control number and the modified configuration data provided by the user are downloaded to the PLD. Finally, the PLD is locked.

摘要翻译： 在自动控制系统中，用户必须被授权修改可编程逻辑器件（PLD）的配置数据。 授权确认后，解锁PLD。 然后，PLD的配置数据和版本控制寄存器的内容被回读和归档，从而在用户需要检索原始数据时提供安全备份。 回读后，版本控制号自动递增。 该增量的版本控制号码和由用户提供的修改的配置数据被下载到PLD。 最后，PLD被锁定。

公开(公告)号：US07302562B1

公开(公告)日：2007-11-27

申请号：US10981931

申请日：2004-11-05

申请人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Mao ,  Rosa M. Y. Chow ,  Pushpasheel Tawade ,  David E. Schweigler ,  Brian D. Erickson ,  Bernardo A. Elayda, III

发明人： Neil G. Jacobson ,  Emigdio M. Flores, Jr. ,  Sanjay Srivastava ,  Bin Dai ,  Sungnien Mao ,  Rosa M. Y. Chow ,  Pushpasheel Tawade ,  David E. Schweigler ,  Brian D. Erickson ,  Bernardo A. Elayda, III

IPC分类号： G06F7/38

CPC分类号： G06F8/65 ,  G06F8/654

摘要： Method and system for a programmable device programmer. The disclosure describes various embodiments for programming a target programmable device by a programmer. In one embodiment, the programmer determines availability of updated configuration data for a hardware component of the programmer. The programmer includes the software component coupled to the hardware component. An update mode of the hardware component is enabled in response to availability of the updated configuration data, and programming of the target programmable device is disabled while the hardware component is in the update mode. A programmable device internal to the hardware component is programmed with the updated configuration data while the hardware component is in the update mode, and the update mode is disabled in response to completion of programming of the at least one programmable device. A target programmable device may then be programmed by the programmer having the updated configuration data.

摘要翻译： 可编程器件编程器的方法和系统。 本公开描述了用于由程序员编程目标可编程器件的各种实施例。 在一个实施例中，编程器确定用于编程器的硬件组件的更新的配置数据的可用性。 程序员包括耦合到硬件组件的软件组件。 响应于更新的配置数据的可用性，启用硬件组件的更新模式，并且当硬件组件处于更新模式时禁用目标可编程设备的编程。 当硬件组件处于更新模式时，硬件组件内部的可编程设备被编程为更新的配置数据，并且响应于至少一个可编程设备的编程完成而禁用更新模式。 然后可以由具有更新的配置数据的编程器对目标可编程设备进行编程。

公开(公告)号：US07091745B1

公开(公告)日：2006-08-15

申请号：US10853403

申请日：2004-05-24

申请人： Neil G. Jacobson

发明人： Neil G. Jacobson

IPC分类号： H03K19/177 ,  H01L25/00 ,  G06F7/38

CPC分类号： H03K19/17748 ,  H03K19/1776 ,  H03K19/17764

摘要： Various approaches for indicating completion of configuration of programmable logic devices are disclosed. In one embodiment, a plurality of configuration memory cells are arranged for storage of a configuration bitstream for implementing a circuit design on the programmable logic circuit. A plurality of configurable resources are coupled to the configuration memory cells, and each configurable resource implements a function based on data stored in one or more of the configuration memory cells coupled to the configurable resource. A logic circuit is coupled to a subset of the configuration memory cells and is configured to assert a done signal in response to states of the subset of the configuration memory cells.

摘要翻译： 公开了用于指示可编程逻辑器件的配置完成的各种方法。 在一个实施例中，布置多个配置存储器单元以存储用于在可编程逻辑电路上实现电路设计的配置位流。 多个可配置资源耦合到配置存储器单元，并且每个可配置资源基于存储在耦合到可配置资源的一个或多个配置存储器单元中的数据来实现功能。 逻辑电路耦合到配置存储器单元的子集，并且被配置为响应于配置存储器单元的子集的状态来断言完成信号。