公开(公告)号：US5838901A

公开(公告)日：1998-11-17

申请号：US692389

申请日：1996-08-05

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00 ,  G06F1/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

公开(公告)号：US5991880A

公开(公告)日：1999-11-23

申请号：US190053

申请日：1998-11-10

申请人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

发明人： Derek R. Curd ,  Neil G. Jacobson ,  Sholeh Diba ,  Napoleon W. Lee ,  Wei-Yi Ku ,  Kameswara K. Rao

IPC分类号： G06F12/14 ,  G06F21/00

CPC分类号： G06F21/76 ,  G06F12/1466

摘要： An overridable data protection mechanism for unlocking/locking a PLD includes a data protect override key register, an input key register, and a comparator. After the user inputs an access code to the input key register, the software program sends an enabling signal to the comparator which in turn compares the bits stored in the data protect override key register and the bits in the input key register. If the bits in the two registers are identical, then the comparator outputs a disable data protect signal, thereby allowing the user to modify the configuration data in that PLD. After an incremented version control number and the new configuration data are downloaded to the PLD, the program sends a disabling signal to the comparator, thereby preventing further modification to the configuration data on that PLD.

摘要翻译： 用于解锁/锁定PLD的可覆盖的数据保护机制包括数据保护覆盖键寄存器，输入键寄存器和比较器。 在用户向输入键寄存器输入访问代码之后，软件程序向比较器发送使能信号，该比较器进一步比较存储在数据保护覆盖键寄存器中的位与输入键寄存器中的位。 如果两个寄存器中的位相同，则比较器输出禁用数据保护信号，从而允许用户修改该PLD中的配置数据。 在增加的版本控制号码和新的配置数据被下载到PLD之后，程序向比较器发送禁用信号，从而防止对该PLD的配置数据的进一步修改。

公开(公告)号：US5661685A

公开(公告)日：1997-08-26

申请号：US533131

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Sholeh Diba ,  Prasad Sastry ,  Mihai G. Statovici ,  Kameswara K. Rao

IPC分类号： G11C16/02 ,  G06F17/50 ,  H03K19/177 ,  G11C7/00

CPC分类号： H03K19/17784 ,  G06F17/5054 ,  H03K19/17704

摘要： An integrated programmable logic device (PLD) includes flash EPROM storage transistors. The PLD includes a multiplexor that selectively provides program, erase, or verify voltages to the storage transistors. The program, erase, and verify voltages may be supplied using external power supplies or may be generated internally by on-chip charge-pump generators. A configurable memory on the PLD is used to adjust the output voltages from each of the on-chip charge-pump generators.

摘要翻译： 集成可编程逻辑器件（PLD）包括闪存EPROM存储晶体管。 PLD包括多路复用器，其选择性地向存储晶体管提供编程，擦除或验证电压。 可以使用外部电源提供程序，擦除和验证电压，或者可以由片上电荷泵发生器内部产生。 PLD上的可配置存储器用于调整每个片上电荷泵发生器的输出电压。

公开(公告)号：US5689516A

公开(公告)日：1997-11-18

申请号：US670916

申请日：1996-06-26

申请人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

发明人： Ronald J. Mack ,  Derek R. Curd ,  Sholeh Diba ,  Napoleon W. Lee ,  Kameswara K. Rao ,  Mihai G. Statovici

IPC分类号： G01R31/3185 ,  G06F11/267 ,  G06F11/00

CPC分类号： G01R31/318516 ,  G01R31/318558 ,  G06F11/2215

摘要： A programmable logic device (PLD) includes test circuitry compatible with the JTAG standard (IEEE Standard 1149.1). The PLD also includes a programmable JTAG-disable bit that can be selectively programmed to disable the JTAG circuitry, leaving the PLD to operate as a conventional, non-JTAG-compatible PLD. The PLD also includes means for testing the JTAG test circuitry to determine whether the JTAG circuitry is defective, and means for programming the JTAG-disable bit to disable the JTAG circuitry if the testing means determines that the JTAG circuitry is defective.

摘要翻译： 可编程逻辑器件（PLD）包括与JTAG标准（IEEE标准1149.1）兼容的测试电路。 PLD还包括一个可编程JTAG禁止位，可以选择性地编程禁止JTAG电路，使PLD能够作为传统的非JTAG兼容PLD运行。 PLD还包括用于测试JTAG测试电路以确定JTAG电路是否有故障的装置，以及如果测试装置确定JTAG电路有故障，则用于编程JTAG禁用位以禁用JTAG电路的装置。

公开(公告)号：US5563827A

公开(公告)日：1996-10-08

申请号：US533412

申请日：1995-09-25

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Wei-Yi Ku ,  Sholeh Diba ,  George Simmons

IPC分类号： G11C16/12 ,  G11C13/00

CPC分类号： G11C16/12

摘要： A wordline driver for a wordline in an integrated programmable logic device (PLD) having flash memory cells. The wordline driver includes an input terminal that accepts a binary wordline input signal, a pass gate coupled to the input terminal and to a mode-control terminal, and an inverter that receives an input from the pass gate or the mode-control terminal, depending on the operating mode of the PLD. The output signal from the inverter is coupled to a multiplexer that selects between that output and a signal from a voltage supply, the signal selected depending on the operating mode of the PLD. The multiplexer outputs the selected signal to the wordline of the PLD.

摘要翻译： 具有闪存单元的集成可编程逻辑器件（PLD）中的字线的字线驱动器。 字线驱动器包括接受二进制字线输入信号的输入端子，耦合到输入端子和模式控制端子的通过栅极，以及根据通路或模式控制端子接收输入的反相器， 在PLD的操作模式下。 来自反相器的输出信号被耦合到多路复用器，该多路复用器在该输出和来自电压源的信号之间选择根据PLD的操作模式选择的信号。 复用器将所选信号输出到PLD的字线。

公开(公告)号：US5949987A

公开(公告)日：1999-09-07

申请号：US48923

申请日：1998-03-26

申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  G05B19/045

CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

摘要： An in-system programming/erasing/verifying structure for non-volatile programmable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

公开(公告)号：US5764076A

公开(公告)日：1998-06-09

申请号：US670472

申请日：1996-06-26

申请人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

发明人： Napoleon W. Lee ,  Derek R. Curd ,  Jeffrey H. Seltzer ,  Jeffrey Goldberg ,  David Chiang ,  Kameswara K. Rao ,  Nicholas Kucharewski, Jr.

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17752 ,  G06F17/5054 ,  H03K19/17704 ,  H03K19/17756

摘要： A complex programmable logic device (PLD) that includes a number of programmable function blocks and an instruction bus for receiving programming instructions. The programming instructions are used to program the function blocks to enable the PLD to perform one or more desired logic functions. The PLD also includes an instruction-blocking circuit that is connected to each of the functional blocks. When directed by a user, the instruction blocking circuit selectively blocks programming instructions on the instruction bus from one or more of the function blocks while allowing the other function blocks to receive the programming instructions. Thus, one or more function blocks in the PLD are reprogrammed without interrupting the operation of the remaining function blocks.

摘要翻译： 一种复杂的可编程逻辑器件（PLD），包括多个可编程功能块和用于接收编程指令的指令总线。 编程指令用于对功能块进行编程，以使PLD能够执行一个或多个所需的逻辑功能。 PLD还包括连接到每个功能块的指令阻塞电路。 当用户指示时，指令分块电路有选择地阻止来自一个或多个功能块的指令总线上的编程指令，同时允许其他功能块接收编程指令。 因此，PLD中的一个或多个功能块被重新编程，而不中断剩余功能块的操作。

公开(公告)号：US5734868A

公开(公告)日：1998-03-31

申请号：US512796

申请日：1995-08-09

申请人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

发明人： Derek R. Curd ,  Kameswara K. Rao ,  Napoleon W. Lee

IPC分类号： H03K19/173 ,  G01R31/3185 ,  G06F17/50 ,  H03K19/177 ,  H03K19/77

CPC分类号： H03K19/1776 ,  G01R31/318516 ,  G06F17/5054 ,  H03K19/17704

摘要： An in-system programing/erasing/verifying structure for non-volatile programable logic devices includes a data input pin, a data output pin, an instruction register, a plurality of data registers including an ISP register, wherein said instruction register and said plurality of data registers are coupled in parallel between said data input pin and said data output pin, and a controller for synchronizing said instruction register and said plurality of data registers. The ISP register includes: an address field, a data field, and a status field. An ISP instruction need only be entered once to program/erase the entire device. Specifically, the address/data packets can be shifted back to back into the ISP register without inserting multiple instructions between each packet at the data input pin, thereby dramatically decreasing the time required to program/erase the entire device in comparison to known ISP methods. Furthermore, the invention provides an efficient method for providing the status (i.e. result), of the ISP operations to either the end-user or the supporting software.

摘要翻译： 用于非易失性可编程逻辑器件的系统内编程/擦除/验证结构包括数据输入引脚，数据输出引脚，指令寄存器，包括ISP寄存器的多个数据寄存器，其中所述指令寄存器和所述多个 数据寄存器并联在所述数据输入引脚和所述数据输出引脚之间，以及用于使所述指令寄存器和所述多个数据寄存器同步的控制器。 ISP寄存器包括：地址字段，数据字段和状态字段。 ISP指令只需输入一次即可对整个设备进行编程/擦除。 具体来说，与已知的ISP方法相比，地址/数据分组可以在数据输入引脚的每个数据包之间插入多个指令，从而大大减少编程/擦除整个器件所需的时间，而将ISP / 此外，本发明提供了一种用于向最终用户或支持软件提供ISP操作的状态（即结果）的有效方法。

公开(公告)号：US5617041A

公开(公告)日：1997-04-01

申请号：US459236

申请日：1995-06-02

申请人： Napoleon W. Lee ,  Wei-Yi Ku ,  Hy V. Nguyen ,  Sholeh Diba

发明人： Napoleon W. Lee ,  Wei-Yi Ku ,  Hy V. Nguyen ,  Sholeh Diba

IPC分类号： G06F17/50 ,  H03K19/177

CPC分类号： H03K19/17764 ,  G06F17/5054 ,  H03K19/17704

摘要： In an EPLD, a feedback switching circuit is provided on a feedback line connected between a macrocell output line and a interconnect matrix wordline, the switching circuit including a memory element and a switch for passing a macrocell output signal from the output line to the interconnect matrix wordline when the memory element is in a first state, and for blocking the macrocell output signal when the memory element is in a second state. This prevents coupling noise in the interconnect matrix because unnecessary feedback signals are prevented from entering the interconnect matrix. In another embodiment, a method is provided in which unused macrocells produce counteractive switching signals in the interconnect matrix to reduce the coupling effect caused by a multiple concurrent switching event. In another embodiment, a sense amplifier is provided in which an EPROM shields coupling between wordlines and bitlines in an interconnect matrix.

摘要翻译： 在EPLD中，在连接在宏单元输出线和互连矩阵字线之间的反馈线上提供反馈开关电路，该开关电路包括用于将宏单元输出信号从输出线传递到互连矩阵的存储元件和开关 当存储元件处于第一状态时，并且当存储元件处于第二状态时阻止宏单元输出信号。 这防止互连矩阵中的耦合噪声，因为不必要的反馈信号被阻止进入互连矩阵。 在另一个实施例中，提供了一种方法，其中未使用的宏单元在互连矩阵中产生反向切换信号，以减少由多个并发切换事件引起的耦合效应。 在另一实施例中，提供一种读出放大器，其中EPROM屏蔽互连矩阵中的字线和位线之间的耦合。

公开(公告)号：US5801548A

公开(公告)日：1998-09-01

申请号：US630321

申请日：1996-04-11

申请人： Napoleon W. Lee ,  Derek R. Curd

发明人： Napoleon W. Lee ,  Derek R. Curd

IPC分类号： H03K19/00 ,  H03K19/0185

CPC分类号： H03K19/0027

摘要： A programmable logic device (PLD) including configurable circuitry for altering the speed-versus-power characteristics of the PLD after production, and for allowing the PLD to selectively operate on either a 3.3-volt or a 5-volt power supply. The configurable circuitry includes an input buffer, an output buffer and a reference generator. The input buffer includes a dedicated P-channel transistor connected in series with a dedicated N-channel transistor, and a plurality of trip-point adjustment transistors which are selectively connected in parallel with the dedicated transistors to adjust the trip-point of the input buffer by altering the N-to-P ratio. The output buffer includes two configurable buffers whose trip-points are also adjustable. A configurable reference generator is also provided for generating a high precision reference voltage which is supplied to the sense amplifiers located in the function blocks and interconnect matrix of the PLD.

摘要翻译： 一种可编程逻辑器件（PLD），包括用于在生产后改变PLD的速度 - 功率特性的可配置电路，并允许PLD选择性地在3.3伏或5伏电源上工作。 可配置电路包括输入缓冲器，输出缓冲器和参考发生器。 输入缓冲器包括与专用N沟道晶体管串联连接的专用P沟道晶体管，以及选择性地与专用晶体管并联的多个跳变点调整晶体管，以调整输入缓冲器的跳变点 通过改变N对P比例。 输出缓冲器包括两个可配置的缓冲器，其跳变点也可调。 还提供了可配置的参考发生器，用于产生高精度参考电压，其被提供给位于PLD的功能块和互连矩阵中的读出放大器。