公开(公告)号：US4659948A

公开(公告)日：1987-04-21

申请号：US514443

申请日：1983-07-18

申请人： Stephen K. Sunter ,  Yachin Afek

发明人： Stephen K. Sunter ,  Yachin Afek

IPC分类号： H03K19/096 ,  H03K17/693 ,  H03K19/177 ,  H03K19/173 ,  H03K19/20

CPC分类号： H03K17/693 ,  H03K19/1772

摘要： A single plane programmable logic array (PLA) using dynamic CMOS logic has switching transistors located at specific locations within a row-column matrix. The transistors within a column are series connected and have their gates common connected in rows. PMOS and NMOS control transistors conduct exclusively to connect output and input ends of the columns respectively to logic 1 or logic 0 in successive phases of a common clock. Control inputs are applied to specific rows. By applying data inputs to column input ends and interconnecting all the column output ends, the PLA is configured to function as a multiplexer. By setting the input end of columns to logic 0 and selectively interconnecting output ends of the columns, the PLA is configured to perform other combinational logic functions.

摘要翻译： 使用动态CMOS逻辑的单平面可编程逻辑阵列（PLA）具有位于行列矩阵内的特定位置处的开关晶体管。 列内的晶体管是串联连接的，并且它们的栅极共同连接成行。 PMOS和NMOS控制晶体管专门用于将列的输出和输入端分别连接到公共时钟的连续相位中的逻辑1或逻辑0。 控制输入​​应用于特定行。 通过将数据输入应用于列输入端并互连所有列输出端，PLA被配置为用作多路复用器。 通过将列的输入端设置为逻辑0并选择性地互连列的输出端，PLA被配置为执行其他组合逻辑功能。

公开(公告)号：US5907589A

公开(公告)日：1999-05-25

申请号：US838592

申请日：1997-04-10

申请人： Vladimir Koifman ,  Yachin Afek

发明人： Vladimir Koifman ,  Yachin Afek

IPC分类号： H03K3/356 ,  H03K21/00

CPC分类号： H03K3/356113

摘要： A frequency divider (50) comprises complementary components (e.g., CMOS transistors) which are placed in two complementary portions (10, 20) with similar structures. The portions are coupled by four lines (131-134). Each line (e.g., 131) is coupled to a pair of transistors including a pull device (e.g., 271) and a hold device (e.g., 291). The devices receives identical signals from another line (e.g., 134) and the input signal X in the same, non-inverted form. The devices have complementary logical functions because of their complementary structures (serial.backslash.parallel) and complementary components (P-FET, N-FET). When a line (e.g., 131) is pulled to a reference line (e.g., 91), contention between the devices is substantially avoided. There is no need to provide the input signal X in a non-inverted and in an inverted form.

摘要翻译： 分频器（50）包括互补部件（例如，CMOS晶体管），其被放置在具有相似结构的两个互补部分（10,20）中。 这些部分连接四行（131-134）。 每一行（例如，131）耦合到一对晶体管，其包括拉设备（例如271）和保持装置（例如，291）。 这些装置以相同的非反相形式从另一条线（例如，134）和输入信号X接收相同的信号。 这些器件具有互补的逻辑功能，因为它们的互补结构（串行+ 544并行）和互补组件（P-FET，N-FET）。 当线（例如131）被拉到参考线（例如，91）时，基本上避免了装置之间的争用。 不需要以非反相和倒置形式提供输入信号X.

公开(公告)号：US5892381A

公开(公告)日：1999-04-06

申请号：US868335

申请日：1997-06-03

申请人： Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

发明人： Vladimir Koifman ,  Yachin Afek ,  Eliezer Sand ,  Kiyoshi Kase

IPC分类号： H03F1/00 ,  G05F1/46 ,  G05F3/16

CPC分类号： G05F1/468

摘要： The rise time of a voltage Vo presented to a load, based on an input voltage Vi provided via an RC filter coupled to the load for removing higher frequency noise on Vo, is substantially reduced by providing a sensor circuit with differential inputs Vi, Vo. The sensor circuit drives a charger circuit coupled to a DC potential and the load so that rapid charging of C to Vo does not depend on R. As Vo approaches Vi, the sensor circuit deactivates the charger circuit to stop further charging and a latch coupled to the sensor circuit shuts off the sensor circuit to reduce power consumption while (Vo.about.Vi)>0. A current mirror buffer is desirably included between the sensor output and the latch for level shifting.

摘要翻译： 基于通过耦合到负载的用于消除Vo上的更高频率噪声的RC滤波器提供的输入电压Vi，提供给负载的电压Vo的上升时间通过向具有差分输入Vi，Vo的传感器电路提供而大大减少。 传感器电路驱动耦合到直流电位和负载的充电器电路，使得C至Vo的快速充电不依赖于R.当Vo接近Vi时，传感器电路使充电器电路停用以停止进一步的充电，并将锁存器耦合到 传感器电路关闭传感器电路，以减少功耗（Vo差分Vi）> 0。 理想地，传感器输出和锁存器之间包括电流镜缓冲器以进行电平转换。

公开(公告)号：US5825246A

公开(公告)日：1998-10-20

申请号：US699255

申请日：1996-08-19

申请人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

发明人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

IPC分类号： H03F3/30 ,  H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/3001

摘要： The amplifier (200) includes an input stage (220) coupled to two output transistors (281, 282) having a common terminal at the output terminal (206) of the amplifier. Class AB operation of the output transistors (281, 282) is possible at a comparatively low supply voltage. In order to obtain such operation, measurement transistors (271, 272) are coupled to the same control input (283, 284) as the output transistors (281, 282). These measurement transistors (271, 272) are serially coupled to a current mirror (260). The quiescent current of the output transistors (281, 282) is measured and used to produce a feedback signal which is superimposed to the control signals.

摘要翻译： 放大器（200）包括耦合到在放大器的输出端（206）处具有公共端的两个输出晶体管（281,282）的输入级（220）。 在相对低的电源电压下，输出晶体管（281,282）的AB类操作是可能的。 为了获得这样的操作，测量晶体管（271,272）耦合到与输出晶体管（281,282）相同的控制输入（283,284）。 这些测量晶体管（271,272）串联耦合到电流镜（260）。 输出晶体管（281,282）的静态电流被测量并用于产生叠加到控制信号的反馈信号。

公开(公告)号：US5603017A

公开(公告)日：1997-02-11

申请号：US309546

申请日：1994-09-20

申请人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

发明人： Gideon Intrater ,  Oved Oz ,  Yachin Afek

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F11/36 ,  G06F13/24 ,  G06F15/78 ,  H04L27/38 ,  G06F1/04

CPC分类号： G06F11/3648 ,  G06F11/3656 ,  G06F11/3664 ,  G06F13/24 ,  G06F15/7842 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/3879 ,  H04L27/38

摘要： An integrated data processing system includes a shared internal bus for transferring both instructions and data. A shared bus interface unit is connected to the shared internal bus and connectable via a shared external bus to a shared external memory array such that instructions and data held in the shared external memory array are transferrable to the shared internal bus via the shared bus interface unit. A general purpose (GP) central processing unit (CPU) is connected to the shared internal bus for retrieving GP instructions. The GP CPU includes an execution unit for executing GP instructions to process data retrieved by the GP CPU from the shared internal bus. A digital signal processor (DSP) module connected to the shared internal bus, the DSP module includes a signal processor for processing an externally-provided digital signal received by the DSP module by executing DSP command-list instructions. Execution of DSP command-list code instructions by the DSP module is independent of and in parallel with execution of GP instructions by the GP CPU. A shared internal memory that holds command-list code instructions and is connected for access by the DSP module for retrieval of command-list code instructions for execution by the DSP module and for access by the GP CPU for storage and retrieval of instructions and data.

摘要翻译： 集成数据处理系统包括用于传送指令和数据的共享内部总线。 共享总线接口单元连接到共享内部总线，并通过共享外部总线连接到共享外部存储器阵列，使得保存在共享外部存储器阵列中的指令和数据可经由共享总线接口单元传送到共享内部总线 。 通用（GP）中央处理单元（CPU）连接到共享内部总线，用于检索GP指令。 GP CPU包括一个执行单元，用于执行GP指令以处理由GP CPU从共享内部总线检索的数据。 连接到共享内部总线的数字信号处理器（DSP）模块，DSP模块包括用于通过执行DSP命令列表指令来处理由DSP模块接收的外部提供的数字信号的信号处理器。 DSP模块执行DSP命令列表代码指令与GP CPU执行GP指令无关，并行执行GP指令。 共享的内部存储器，其保存命令列表代码指令，并且被连接以供DSP模块访问，用于检索由DSP模块执行的命令列表代码指令，并由GP CPU访问用于存储和检索指令和数据。

公开(公告)号：US5514999A

公开(公告)日：1996-05-07

申请号：US327723

申请日：1994-10-24

申请人： Vladimir Koifman ,  Yachin Afek

发明人： Vladimir Koifman ,  Yachin Afek

IPC分类号： H03M1/44 ,  H03F3/45 ,  H03H19/00 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12 ,  H03M3/02 ,  H04L25/02 ,  H03F1/14

CPC分类号： H04L25/0272 ,  H03F3/45479 ,  H03M1/0682 ,  H03M1/0863 ,  H04L25/0292 ,  H03F2200/331 ,  H03M1/12

摘要： A differential switched capacitor circuit (6) for sampling a differential input signal (IP, IM) in different sampling phases (PHI0, PHI1) and for correcting errors at an output thereof, comprises:m switched capacitor stages (8-16) coupled in a chain, a first stage (8) being coupled to the output of the circuit, each of the m switched capacitor stages (8-16) being coupled to an adjacent stage in the chain depending on the sampling phase such that a charge representative of the error is equally shared between adjacent stages in the chain and wherein the mth stage (16) is selectively coupled to an end node so as to cancel the charge thereon, whereby after a number of sampling phases the error at the output is substantially reduced by a factor of up to 1/m.

摘要翻译： 一种差分开关电容器电路（6），用于对不同采样相位（PHI0，PHI1）中的差分输入信号（IP，IM）进行采样，并用于在其输出端校正误差，包括：m个开关电容器级（8-16） 链路，第一级（8）耦合到电路的输出端，m个开关电容器级（8-16）中的每一个根据采样相位耦合到链中的相邻级，使得代表 误差在链中的相邻级之间同等地共享，并且其中第m级（16）选择性地耦合到端节点以消除其上的电荷，由此在多个采样相位之后，输出端的误差被大大地减小 高达1 / m的因子。

公开(公告)号：US06570947B1

公开(公告)日：2003-05-27

申请号：US09404933

申请日：1999-09-24

申请人： Eliav Zipper ,  Michael Zarubinsky ,  Yachin Afek

发明人： Eliav Zipper ,  Michael Zarubinsky ,  Yachin Afek

IPC分类号： H03D324

CPC分类号： H03L7/093 ,  H03L7/107 ,  H03L7/18

摘要： A phase lock loop having an bandwidth that does not depend upon N. The phase lock loop comprising: a controlled oscillator, a frequency divider by N, a phase detector for producing an error signal ER, and an adjustable converter, coupled to the phase detector and to the current controlled oscillator, for receiving ER and providing the controlled oscillator a control signal such that that the (Fico/N) ranges between a minimum value of Fmin and a maximal value of Fmax, wherein Fref=(Fmin+Fmax)/2.

摘要翻译： 具有不依赖于N的带宽的锁相环。锁相环包括：受控振荡器，N分频器，用于产生误差信号ER的相位检测器和可调整转换器，耦合到相位检测器 以及当前受控振荡器，用于接收ER并向控制振荡器提供控制信号，使得（Fico / N）范围在最小值Fmin和最大值Fmax之间，其中Fref =（Fmin + Fmax）/ 2。

公开(公告)号：US5828264A

公开(公告)日：1998-10-27

申请号：US569038

申请日：1995-12-07

申请人： Vladimir Koifman ,  Yachin Afek

发明人： Vladimir Koifman ,  Yachin Afek

IPC分类号： H03F1/08 ,  H03F1/30 ,  H03F1/34

CPC分类号： H03F1/086

摘要： A two stage operational amplifier circuit comprises a first stage (31) having an input (2, 4) and an output, and a second stage (33) having an input and an output (19). The second stage input is coupled to receive the first stage output. A feedback path (41, 45, 47, 51) is coupled between the output and the input of the second stage. The feedback path (41, 45, 47, 51) comprises a low-frequency compensation path (41, 45) and high-frequency compensation path (45, 47, 51). The feedback path (41, 45, 47, 51) is compensated such that the frequency response of the second output of the second stage is substantially 6 dB per octave throughout the high-frequency region.

摘要翻译： 两级运算放大器电路包括具有输入（2,4）和输出的第一级（31）和具有输入和输出（19）的第二级（33）。 第二级输入被耦合以接收第一级输出。 反馈路径（41,45,47,51）耦合在第二级的输出和输入之间。 反馈路径（41,45,47,51）包括低频补偿路径（41,45）和高频补偿路径（45,47,51）。 补偿反馈路径（41,45,47,51），使得第二级的第二输出的频率响应在整个高频区域内基本上是每倍频程6dB。

公开(公告)号：US5790063A

公开(公告)日：1998-08-04

申请号：US767052

申请日：1996-12-16

申请人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

发明人： Vladimir Koifman ,  Yachin Afek ,  Israel Kashat

IPC分类号： H03M3/02 ,  H03M1/46

CPC分类号： H03M3/348 ,  H03M3/464

摘要： An analog-to-digital converter is introduced which operates as an oversampled delta-sigma converter. The converter is implemented fully differentially, having doubled integrator capacitors (130, 230), comparators (180, 280), and feedback units (160, 260). In order to reduce the influence of parasitic capacities, the feedback units (160, 260) comprise cascoded switches (171-179). Internal auxiliary signals for controlling the feedback units (160, 260) return to zero at clock frequency. The converter can be used in an integrated signal processing circuit having analog and digital domains on one chip. The capacitors (130, 230) itself are implemented by MOS transistors with the same single poly process as the rest of the circuit. In a second embodiment of the invention, the analog-to-digital converter (500) comprises multiple comparators (580, 572, 573, 574), dynamic matching circuits (801, 802). The comparators (572, 573, 574) can received dithered input signals.

摘要翻译： 引入了一个模拟 - 数字转换器，其作为过采样的delta-sigma转换器工作。 该转换器完全不同地实现，具有倍增的积分电容器（130,230），比较器（180,280）和反馈单元（160,260）。 为了减少寄生电容的影响，反馈单元（160,260）包括级联开关（171-179）。 用于控制反馈单元（160,260）的内部辅助信号在时钟频率下恢复为零。 该转换器可用于在一个芯片上具有模拟和数字域的集成信号处理电路。 电容器（130,230）本身由具有与电路的其余部分相同的单个多晶硅工艺的MOS晶体管实现。 在本发明的第二实施例中，模数转换器（500）包括多个比较器（580,572,573,574），动态匹配电路（801,802）。 比较器（572,573,574）可以接收抖动输入信号。

公开(公告)号：US5631589A

公开(公告)日：1997-05-20

申请号：US324073

申请日：1994-10-14

申请人： Yachin Afek ,  Claudine Tordjman ,  Ricardo Berger

发明人： Yachin Afek ,  Claudine Tordjman ,  Ricardo Berger

IPC分类号： H03K19/003 ,  H03B1/00

CPC分类号： H03K19/00361

摘要： A transition control circuit (2) for controlling the transitions of an output signal, at an output node (8) of a driver circuit, in dependence on the logic state of an input signal at an input node (10). The output signal being switchable between a first logic state and a second logic state. The transition control circuit (2) comprises first means (16) and second means (14). The first means (16) is enabled when the output signal has the first logic state and the input signal has the second logic state, and is disabled when the output signal has the second logic state or the input signal has the first logic state. Once enabled, the first means (16) couples the output node (8) to a first supply line (GNDA) whereby the output signal switches to the second logic state. The second means (14) is enabled when the output signal has the second logic state and the input signal has the second logic state, and is disabled when the output signal has the first logic state or the input signal has the first logic state. Once enabled, the second means (14) couples the output node to a second supply line (GNDB) whereby the output signal is held in the second logic state until the next transition of the input signal.

摘要翻译： 一种用于根据输入节点（10）上的输入信号的逻辑状态，在驱动电路的输出节点（8）处控制输出信号的转变的转移控制电路（2）。 输出信号可在第一逻辑状态和第二逻辑状态之间切换。 过渡控制电路（2）包括第一装置（16）和第二装置（14）。 当输出信号具有第一逻辑状态并且输入信号具有第二逻辑状态时，第一装置（16）被使能，并且当输出信号具有第二逻辑状态或输入信号具有第一逻辑状态时被禁用。 一旦使能，第一装置（16）将输出节点（8）耦合到第一电源线（GNDA），由此输出信号切换到第二逻辑状态。 当输出信号具有第二逻辑状态并且输入信号具有第二逻辑状态时，第二装置（14）被使能，并且当输出信号具有第一逻辑状态或输入信号具有第一逻辑状态时被禁用。 一旦使能，第二装置（14）将输出节点耦合到第二电源线（GNDB），由此输出信号保持在第二逻辑状态直到输入信号的下一个转换。