公开(公告)号：US6162689A

公开(公告)日：2000-12-19

申请号：US187231

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/266 ,  H01L21/285 ,  H01L21/336 ,  H01L29/417

CPC分类号： H01L29/66598 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659

摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e., above the shallower junctions) does not react to form cobalt silicide, and is thereafter removed. The present invention provides ultra-shallow source-drain junctions near the gates for improved electrical characteristics, and deeper junctions away from the gates, with cobalt silicide contacts above only the deeper junction portions to avoid junction leakage, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 实例包括形成场氧化物区域，栅极，间隔物和轻掺杂的植入物，然后在衬底上沉积氧化物层。 掩模氧化层以保护位于栅极附近的氧化物层的部分，期望具有浅结，然后蚀刻以暴露要形成硅化物触点的预期源/漏区的部分。 此后，进行高剂量源/漏注入，以与氧化物层被蚀刻掉的衬底形成深的源极/漏极结，并且在栅极附近形成较浅的结，其中植入物必须在 到达基板。 此后沉积一层钴，并且仅在深源极/漏极接合处进行硅化以形成金属硅化物接触，而氧化物层上的钴（即，较浅的接合点上方）不反应形成硅化钴，并且是 此后取出。 本发明提供了栅极附近的超浅源极 - 漏极结，用于改善电气特性，以及远离栅极的较深的结，钴硅化物接触仅在较深的接合部分上方，以避免结漏电，从而便于可靠的器件缩放。

公开(公告)号：US6096599A

公开(公告)日：2000-08-01

申请号：US187521

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  Y10S438/923

摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高度完整的浅源极/漏极结。 实施例包括在目标源极/漏极区域上的衬底上沉积钴层，在钴上沉积钛或氮化钛的覆盖层，在覆盖层上沉积掺杂的膜，并通过快速热退火进行硅化， 形成低电阻率的硅化钴，并且通过硅化钴将掺杂的膜中的杂质扩散到衬底中，以形成在硅化钴界面下面延伸到衬底中的恒定深度的结。 与硅化钴/硅界面自对准的源极/漏极结的形成防止结漏，同时允许在最佳厚度下形成硅化钴触点，从而便于可靠的器件缩放。

公开(公告)号：US06238986B1

公开(公告)日：2001-05-29

申请号：US09187427

申请日：1998-11-06

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L2128

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665

摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness to avoid parasitic series resistances, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高度完整的浅源极/漏极结。 一层钴和钛或氮化钛的覆盖层沉积在预期的源极/漏极区域上的衬底上，随后进行硅化。 实施例包括低温快速热退火以形成高电阻率相硅化钴，去除覆盖层，在第一相钴硅化物上沉积掺杂膜，并且通过高温快速热退火加热以形成低 电阻的硅化钴，其中来自掺杂膜的杂质通过硅化钴扩散到衬底中以形成具有在硅化钴/硅衬底界面下方延伸到衬底中的连续恒定深度的接合的源/漏区。 在另一个实施例中，在形成低电阻相钴硅化物之后，杂质从掺杂膜扩散以形成源/漏区和自对准结。 与硅化钴/硅衬底界面自对准的源极/漏极结的形成可防止结合泄漏，同时允许以最佳厚度形成硅化钴触点，以避免寄生串联电阻，从而便于可靠的器件缩放。

公开(公告)号：US06169005A

公开(公告)日：2001-01-02

申请号：US09318824

申请日：1999-05-26

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21386

CPC分类号： H01L21/28518 ,  H01L21/2257 ,  H01L21/76895 ,  H01L29/665

摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface. The consumption of the amorphous silicon film during silicidation, which results in less consumption of substrate silicon, and formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface, enables the formation of ultra-shallow source/drain junctions without junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 这些是通过在目标源极/漏极区域上的衬底上沉积钴层而在钴上沉积掺杂的非晶硅膜形成的。 通过快速热退火进行硅化，以形成低电阻的硅化钴，同时消耗非晶硅膜并将杂质从掺杂的非晶硅膜通过硅化钴扩散到衬底中。 杂质的扩散形成延伸到衬底中的浅结，在硅化钴/硅衬底界面下方基本上恒定的深度。 在硅化期间，非晶硅膜的消耗导致较少的衬底硅消耗，以及与硅化钴/硅衬底界面自对准的源极/漏极结的形成使得能够形成超浅源极/漏极结而不形成 结点泄漏，同时允许以最佳厚度形成钴硅化物触点，从而便于可靠的器件缩放。

公开(公告)号：US6100145A

公开(公告)日：2000-08-08

申请号：US186073

申请日：1998-11-05

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul Raymond Besser

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656

摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Field oxide regions, gates, spacers, and source/drain implants are initially formed. A layer of silicon is then deposited. A protective non-contuctive film is then formed and anisotropically etched to expose the silicon layer on the source/drain regions and the top surfaces of the gates, and to form protective spacers on the edges of the field oxide regions and on the side surfaces of the gates. A layer of cobalt is thereafter deposited and silicidation is performed, as by rapid thermal annealing, to form a low-resistance cobalt silicide while consuming the silicon film. The consumption of the silicon film during silicidation results in less consumption of substrate silicon, thereby enabling the formation of ultra-shallow source/drain junctions without junction leakage, allowing the formation of cobalt silicide contacts at optimum thickness and facilitating reliable device scaling.

摘要翻译： 使用硅化钴接触形成高完整性超浅源极/漏极结。 初始形成场氧化物区域，栅极，间隔物和源/漏植入物。 然后沉积一层硅。 然后形成保护性非导电膜，并进行各向异性蚀刻，以暴露栅极/源极区域和栅极顶表面上的硅层，并在场氧化物区域的边缘和侧表面上形成保护隔离物 大门。 此后沉积一层钴，通过快速热退火进行硅化，以在消耗硅膜的同时形成低电阻的硅化钴。 在硅化期间硅膜的消耗导致较少的衬底硅消耗，从而能够形成没有结漏的超浅源极/漏极结，从而允许以最佳厚度形成钴硅化物触点并促进可靠的器件缩放。

公开(公告)号：US06380040B1

公开(公告)日：2002-04-30

申请号：US09629883

申请日：2000-08-01

申请人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul R. Besser

发明人： Nick Kepler ,  Karsten Wieczorek ,  Larry Wang ,  Paul R. Besser

IPC分类号： H01L21386

CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823878

摘要： High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.

摘要翻译： 高完整性的硅化钴触点形成有浅的源极/漏极结。 实施例包括在期望的源极/漏极区域上方的衬底上沉积钴层，随后在阻止杂质向环境的扩散的环境中硅化处理期间或之后从掺杂膜上硅化并扩散杂质。 所得的源极/漏极结与钴硅化物/硅衬底界面自对准，从而防止结漏电，同时有利地使钴硅化物触点形成最佳厚度以避免寄生串联电阻。 对硅化钴/硅衬底界面的自对准源极/漏极结的形成有利于可靠的器件缩放，同时避免杂质向环境的不期望的扩散确保了源极/漏极区域的充分掺杂。

公开(公告)号：US06150243A

公开(公告)日：2000-11-21

申请号：US186065

申请日：1998-11-05

申请人： Karsten Wieczorek ,  Nick Kepler ,  Larry Wang ,  Paul R. Besser

发明人： Karsten Wieczorek ,  Nick Kepler ,  Larry Wang ,  Paul R. Besser

IPC分类号： H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L21/8238

CPC分类号： H01L21/28061 ,  H01L21/2255 ,  H01L21/2257 ,  H01L21/2652 ,  H01L29/665 ,  H01L29/6659

摘要： Self-aligned, ultra-shallow, heavily-doped source and drain regions of a MOS device are formed by implanting dopant containing ions in a dielectric layer formed on metal silicide layer portions on regions of a silicon-containing substrate where source and drain regions are to be formed in a silicon-containing substrate. Thermal treatment of the implanted dielectric layer results in out-diffusion of dopant through the metal silicide layer and into the region of the silicon-containing substrate immediately below the metal silicide layer portions, thereby forming heavily doped source and drain regions having an ultra-shallow junction spaced apart from the metal silicide/silicon substrate interface by a substantially uniform distance.

摘要翻译： MOS器件的自对准，超浅，重掺杂的源极和漏极区域通过在含硅衬底的金属硅化物层部分上形成的电介质层中注入掺杂剂，形成源极和漏极区域 以形成在含硅衬底中。 注入的介电层的热处理导致掺杂剂通过金属硅化物层的外扩散并进入紧邻金属硅化物层部分的含硅衬底区域，由此形成具有超浅的重掺杂源极和漏极区 结合金属硅化物/硅衬底界面与基本均匀的距离间隔开。

公开(公告)号：US6162699A

公开(公告)日：2000-12-19

申请号：US181561

申请日：1998-10-29

申请人： Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Larry Wang ,  Nick Kepler ,  Olov Karlsson ,  Basab Bandyopadhyay ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224 ,  Y10S438/942 ,  Y10S438/945

摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.

摘要翻译： 用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构 区域层，多晶硅层和局部互连（LI）层。 一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。 一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。 然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。 然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。 所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

公开(公告)号：US06380047B1

公开(公告)日：2002-04-30

申请号：US09634990

申请日：2000-08-08

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

摘要翻译： 使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料 沟渠 然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。 由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。 此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

公开(公告)号：US6124183A

公开(公告)日：2000-09-26

申请号：US992490

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分 绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。 由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。