摘要:
A gain control system for a gain stage of a wireless communication system includes a gain control module and a mode selection module. The gain control module is operable in automatic gain control (AGC) and manual gain control (MGC) modes. The mode selection module checks the presence of first user-data in the first sub-frame based on a received signal strength indication (RSSI) value and/or a decibel amplitude level relative to full scale (dBFS) value, the presence of second user-data in a second sub-frame subsequent to the first sub-frame based on an advance information, calculates an estimated signal power level, and configures the gain control module in one of the AGC and MGC modes. Based on the mode, the gain control module provides a gain value to the gain stage.
摘要:
Solutions are provided that allow a network device to apply flow control on the MAC layer while taking into account the priority of the frame of traffic. This may be accomplished by generating a frame indicating that traffic flow should be paused, while utilizing a new opcode value, or alternatively by utilizing a new type/length value (possibly combined with a new opcode value). A receiving device may then examine the fields of the frame to determine whether it should use priority-based pausing, and then examine other fields to determine which priority-levels to pause and for how long. This allows for improved efficiency in flow control on the MAC layer.
摘要:
The present disclosure includes an integrated full-duplex transceiver, which may be implemented on a single substrate or die. A single substrate may in turn, comprise, an I/O port configured for full-duplex operation, a transmit portion and a receive portion, a first mixer for up-converting a transmit signal, a second mixer for down-converting a receive signal, a first independently tunable local oscillator that drives the first mixer, and a second independently tunable local oscillator that drives the second mixer. The first independently tunable oscillator may facilitate up-conversion of a transmit IF signal, while a second independently tunable oscillator may facilitate down-conversion of a receive RF signal.
摘要:
The present invention provides a method and system of providing minimization drive test (MDT) measurement information to a base station in a wireless communication network. In one embodiment, a method includes indicating availability of MDT measurement information logged by user equipment to a base station in a wireless network environment. The method further includes receiving an information request message to transfer the MDT measurement information in response to the indication. The method includes transmitting an information response message including at least a portion of the MDT measurement information to the base station, where the information response message indicates whether any portion of MDT measurement information is leftover with the user equipment. The method then includes repeating the above steps of receiving and transmitting till the entire MDT measurement information is transferred to the base station.
摘要:
A circuit includes an input node configured to receive a test address input signal and circuitry configured to generate, from a first part of the test address input signal, a first address signal that selects a first address of a first part of a circuit to be tested and further generate, from a second part of the test address input signal, a second signal configured to select a second part of the circuit to be tested. Test circuitry is then configured to use the first address and the second part in a test mode.
摘要:
Method and apparatus are provided for communicating availability and removal of one or more CCs in a cell. The one or more CCs that are available in the cell of a wireless communication network are determined, or a need to release one or more CCs that are active in the cell of a wireless communication network is detected. Availability of or the need to release the one or more CCs in the cell is communicated to a plurality of mobile stations. Each of the plurality of mobile stations is allowed to use or de-activate the one or more CCs in the cell.
摘要:
A circuit for processing a clock signal including first and second clock edges of different polarities, the circuit including an inverter for inverting a first clock edge to generate an inverted first clock edge and inverting a second clock edge to generate an inverted second clock edge; a first pass gate for receiving the inverted clock edge and outputting a first trigger signal of a first polarity; and a second pass gate for receiving the second clock edge and outputting a second trigger signal of the first polarity, wherein the second pass gate is controlled to open responsive to the inverted second clock edge; whereby the delay between the first clock edge and the first trigger signal is substantially equal to the delay between the second clock edge and second trigger signal.
摘要:
A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.
摘要:
A system and method are provided for warming a network intermediary (e.g., a proxy, a transaction accelerator) to enable it to provide effective optimization (e.g., data reduction) without a cold start. When a pair of network intermediaries cooperate to optimize a communication connection (e.g., between a client and a server), either or both intermediaries may form branch channels with one or more peers. Via these branch channels, the intermediaries may forward optimization information such as data references received from the other intermediary (i.e., in place of data segments, as part of a data reduction scheme), and/or resolve unknown references.
摘要:
A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.