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18 条记录 (耗时 0.026 秒)

    Amplifier circuit, antenna module, and radio communication device
    2.
    发明授权
    Amplifier circuit, antenna module, and radio communication device 有权
    放大器电路，天线模块和无线电通信设备

    公开(公告)号：US09473199B2

    公开(公告)日：2016-10-18

    申请号：US14762060

    申请日：2014-02-04

    申请人： Masaaki Tsuji ,  Koji Kawahata ,  Nobunari Tsukamoto ,  Takashi Otsuki

    发明人： Masaaki Tsuji ,  Koji Kawahata ,  Nobunari Tsukamoto ,  Takashi Otsuki

    IPC分类号： H04B5/02 ,  H04B1/59 ,  H03F3/189 ,  H03F1/56 ,  H04B1/24 ,  H04B1/04 ,  H04B1/18

    CPC分类号： H04B1/59 ,  H03F1/56 ,  H03F3/189 ,  H03F2200/255 ,  H03F2200/451 ,  H04B1/0458 ,  H04B1/18 ,  H04B1/24 ,  H04B5/02

    摘要： An amplifier circuit performs an amplification of a carrier signal received by a transmitting and receiving unit. The amplifier circuit includes an impedance matching circuit that performs matching of an impedance of the amplifier circuit when the transmitting and receiving unit and the amplifier circuit are connected. A superposition wave generating unit generates a superposition wave which is superimposed on the received carrier signal. A driver outputs an amplified carrier signal which is obtained by adding the superposition wave to the received carrier signal. An amplitude detecting unit detects whether the received carrier signal is a predetermined carrier signal superimposed with a predetermined communication signal, based on changes of an amplitude value of the received carrier signal. When the predetermined carrier signal is detected, the amplifier circuit outputs the amplified carrier signal.

    摘要翻译： 放大器电路对由发​​送和接收单元接收的载波信号进行放大。 放大电路包括阻抗匹配电路，当连接发射和接收单元和放大器电路时，其执行放大器电路的阻抗匹配。 叠加波生成单元生成叠加在所接收的载波信号上的叠加波。 驱动器输出通过将叠加波加到接收到的载波信号而获得的放大载波信号。 振幅检测单元基于所接收的载波信号的振幅值的变化来检测所接收的载波信号是否是与预定通信信号叠加的预定载波信号。 当检测到预定的载波信号时，放大器电路输出放大的载波信号。

    Differential signal output device
    5.
    发明申请
    Differential signal output device 有权
    差分信号输出装置

    公开(公告)号：US20090046784A1

    公开(公告)日：2009-02-19

    申请号：US12222523

    申请日：2008-08-11

    申请人： Nobunari Tsukamoto ,  Hidetoshi Ema

    发明人： Nobunari Tsukamoto ,  Hidetoshi Ema

    IPC分类号： H04B14/06

    CPC分类号： G06F13/4291

    摘要： A differential signal output device is disclosed that outputs transmission data as a differential signal. The device includes a first differential signal generation circuit that amplifies a signal representing the transmission data and generates the differential signal from the amplified signal; a dummy data generation circuit that is synchronized with a reference clock of the transmission data and generates dummy data that change only in a bit where the transmission data do not change; and a second differential signal generation circuit that amplifies a signal representing the dummy data and generates another differential signal from the amplified signal.

    摘要翻译： 公开了一种输出传输数据作为差分信号的差分信号输出装置。 该装置包括：第一差分信号生成电路，其放大表示发送数据的信号，并从放大信号生成差分信号; 与发送数据的基准时钟同步的伪数据生成电路，生成仅在发送数据不发生变化的比特中变化的伪数据; 以及第二差分信号生成电路，其对表示所述虚拟数据的信号进行放大，并从所述放大信号生成另一差分信号。

    OVERSAMPLING CIRCUIT AND OVERSAMPLING METHOD
    6.
    发明申请
    OVERSAMPLING CIRCUIT AND OVERSAMPLING METHOD 有权
    过电压和过压保护方法

    公开(公告)号：US20080056420A1

    公开(公告)日：2008-03-06

    申请号：US11845416

    申请日：2007-08-27

    申请人： Nobunari Tsukamoto ,  Hidetoshi Ema

    发明人： Nobunari Tsukamoto ,  Hidetoshi Ema

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0338

    摘要： A multiphase delay unit causes a different delay time to a reference clock to generate a multiphase clock having a different phase. A multiphase sampling unit samples the input signal using the multiphase clock, and outputs multiphase sampling data. A phase selecting unit detects a phase relation of the multiphase clock using the multiphase sampling data, and selects output data from the multiphase sampling data based on data obtained by detecting the phase relation of the multiphase clock.

    摘要翻译： 多相延迟单元对参考时钟产生不同的延迟时间以产生具有不同相位的多相时钟。 多相采样单元使用多相时钟采样输入信号，并输出多相采样数据。 相位选择单元使用多相采样数据检测多相时钟的相位关系，并且基于通过检测多相时钟的相位关系而获得的数据，从多相采样数据中选择输出数据。

    WIRELESS COMMUNICATION DEVICE AND MOBILE TERMINAL
    7.
    发明申请
    WIRELESS COMMUNICATION DEVICE AND MOBILE TERMINAL 审中-公开
    无线通信设备和移动终端

    公开(公告)号：US20160197651A1

    公开(公告)日：2016-07-07

    申请号：US14976612

    申请日：2015-12-21

    申请人： Nobunari Tsukamoto

    发明人： Nobunari Tsukamoto

    IPC分类号： H04B5/00 ,  H04W4/02 ,  H04W4/00

    CPC分类号： H04W4/026 ,  H04B5/0081 ,  H04B7/0814 ,  H04W4/80

    摘要： A wireless communication device that communicates wirelessly with other device includes a first antenna, a second antenna, a measurer, and a selector. The first antenna is a loop or loops of coiled wire, and the first antenna is disposed on a substrate so that a rotation axis of the first antenna is orthogonal to the substrate. The second antenna is a loop or loops of coiled wire, and the second antenna is disposed on the substrate so that a rotation axis of the second antenna is parallel to the substrate. The measurer measures signals respectively generated in the first antenna and the second antenna, in accordance with a positional relationship between the other device and the wireless communication device. The selector selects one of the first antenna and the second antenna as an antenna for communicating with the other device, in accordance with amplitude of the measured signals.

    摘要翻译： 与其他设备无线通信的无线通信设备包括第一天线，第二天线，测量器和选择器。 第一天线是线圈的环形圈，并且第一天线设置在基板上，使得第一天线的旋转轴线与基板正交。 第二天线是线圈的环或环，并且第二天线设置在基板上，使得第二天线的旋转轴线平行于基板。 测量器根据其他设备和无线通信设备之间的位置关系来测量分别在第一天线和第二天线中产生的信号。 选择器根据测量信号的幅度选择第一天线和第二天线中的一个作为与另一设备进行通信的天线。

    Data processing apparatus
    8.
    发明授权
    Data processing apparatus 有权
    数据处理装置

    公开(公告)号：US08243865B2

    公开(公告)日：2012-08-14

    申请号：US11763663

    申请日：2007-06-15

    申请人： Nobunari Tsukamoto ,  Hidetoshi Ema

    发明人： Nobunari Tsukamoto ,  Hidetoshi Ema

    IPC分类号： H04L7/00

    CPC分类号： H03M7/3048

    摘要： A disclosed data processing apparatus includes: a binarization unit binarizing input data based on a threshold voltage; a capture unit capturing data from a binary output binarized by the binarization unit; a duty cycle detection unit detecting a duty cycle of the binary output; and a control unit controlling a level of the input data based on the duty cycle detected by the duty cycle detection unit.

    摘要翻译： 公开的数据处理装置包括：二值化单元，基于阈值电压二值化输入数据; 捕获单元，从由二值化单元二值化的二进制输出中获取数据; 占空比检测单元，检测二进制输出的占空比; 以及控制单元，其基于由占空比检测单元检测到的占空比来控制输入数据的电平。

    FM-AM demodulator and control method therefor
    9.
    发明授权
    FM-AM demodulator and control method therefor 失效
    FM-AM解调器及其控制方法

    公开(公告)号：US08213892B2

    公开(公告)日：2012-07-03

    申请号：US12685960

    申请日：2010-01-12

    申请人： Nobunari Tsukamoto

    发明人： Nobunari Tsukamoto

    IPC分类号： H04B1/10

    CPC分类号： H04B1/30 ,  H03D1/00 ,  H03D3/009

    摘要： A FM-AM demodulator includes a FM signal amplifier, a local oscillator, an image oscillator, a first selector, a first orthogonal mixer, an AM signal amplifier, a first frequency divider, a second frequency divider, a second selector, a second orthogonal mixer, a third selector, a first filter, a first amplifier, a fourth selector, a second filter, a second amplifier, a first gain controller, an I/Q compensation unit, an IF oscillator, a third orthogonal mixer, an adder, a channel filter configured to extract a signal with a predetermined frequency band output from the adder, a third amplifier, a second gain controller, a demodulator, and an I/Q compensation controller configured to generate an I/Q compensation signal to use for adjusting phase and gain of the I signal used in an I/Q compensation unit by detecting amplitude of the output signal from the demodulator, and output the generated signal to the I/Q compensation unit.

    摘要翻译： FM-AM解调器包括FM信号放大器，本地振荡器，图像振荡器，第一选择器，第一正交混频器，AM信号放大器，第一分频器，第二分频器，第二选择器，第二正交 混频器，第三选择器，第一滤波器，第一放大器，第四选择器，第二滤波器，第二放大器，第一增益控制器，I / Q补偿单元，IF振荡器，第三正交混频器， 信道滤波器，被配置为从加法器输出的预定频带提取信号;第三放大器，第二增益控制器，解调器和I / Q补偿控制器，被配置为产生用于调整的I / Q补偿信号 通过检测来自解调器的输出信号的振幅，在I / Q补偿单元中使用的I信号的相位和增益，并将产生的信号输出到I / Q补偿单元。

    Low voltage differential signaling driver
    10.
    发明授权
    Low voltage differential signaling driver 有权

    公开(公告)号：US10298419B2

    公开(公告)日：2019-05-21

    申请号：US15795927

    申请日：2017-10-27

    申请人： Yuji Watabe ,  Hiroaki Kyogoku ,  Nobunari Tsukamoto

    发明人： Yuji Watabe ,  Hiroaki Kyogoku ,  Nobunari Tsukamoto

    IPC分类号： H03L5/00 ,  H04L25/02 ,  H03K19/0185 ,  H03K17/687 ,  H03L7/093 ,  G06F1/06 ,  H03K5/135 ,  H03L7/081

    摘要： A low voltage differential signaling driver includes at least one output circuit, a first control circuit, and a second control circuit. The output circuit includes a first input terminal to receive a first input signal, a second input terminal to receive a second input signal, a first output terminal to output a first output signal, a second output terminal to output a second output signal, and first to sixth transistors. The first control circuit controls a voltage of a control terminal of the first transistor to make a voltage of the first output signal equal to a first reference voltage when the first input signal has a first value. The second control circuit controls a voltage of a control terminal of the second transistor to make the voltage of the first output signal equal to a second reference voltage when the first input signal has a second value.