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162 条记录 (耗时 0.023 秒)

    Semiconductor device and method for fabricating same
    2.
    发明申请
    Semiconductor device and method for fabricating same 失效
    半导体装置及其制造方法

    公开(公告)号：US20060105582A1

    公开(公告)日：2006-05-18

    申请号：US11250439

    申请日：2005-10-17

    申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

    发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28202 ,  H01L29/513 ,  H01L29/518

    摘要： A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.

    摘要翻译： 提供了一种方法：在硅衬底的表面上排列氮原子; 在氢气氛中进行热处理，使得存在于硅衬底表面上的氮原子和硅原子处于三配位键状态; 并且在硅衬底上形成具有氮原子的三配位键状态并保持硅原子的氧化硅膜。

    Fin transistor
    4.
    发明授权
    Fin transistor 有权
    鳍晶体管

    公开(公告)号：US07989856B2

    公开(公告)日：2011-08-02

    申请号：US12335701

    申请日：2008-12-16

    申请人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

    发明人： Masakazu Goto ,  Nobutoshi Aoki ,  Takashi Izumida ,  Kimitoshi Okano ,  Satoshi Inaba ,  Ichiro Mizushima

    IPC分类号： H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/7845

    摘要： A fin transistor includes: a substrate; a plurality of semiconductor fins formed on the substrate; a gate electrode covering a channel region of the semiconductor fins; and a member as a stress source for the semiconductor fins included in a region of the gate electrode and the region provided between the semiconductor fins, and the member being made of a different material from the gate electrode.

    摘要翻译： 翅片晶体管包括：衬底; 形成在所述基板上的多个半导体翅片; 覆盖半导体鳍片的沟道区域的栅电极; 以及作为用于包括在栅极电极的区域中的半导体鳍片的应力源的构件和设置在半导体鳍片之间的区域，并且该构件由与栅电极不同的材料制成。

    Semiconductor device and method for fabricating same
    5.
    发明授权
    Semiconductor device and method for fabricating same 失效
    半导体装置及其制造方法

    公开(公告)号：US07358198B2

    公开(公告)日：2008-04-15

    申请号：US11250439

    申请日：2005-10-17

    申请人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

    发明人： Nobutoshi Aoki ,  Koichi Kato ,  Katsuyuki Sekine ,  Ichiro Mizushima

    IPC分类号： H01L21/31

    CPC分类号： H01L21/28202 ,  H01L29/513 ,  H01L29/518

    摘要： A method is provided with: arranging nitrogen atoms on a surface of a silicon substrate; performing a heat treatment in a hydrogen atmosphere so that the nitrogen atoms and silicon atoms existing on the surface of the silicon substrate are brought into a three-coordinate bond state; and forming a silicon oxide film on the silicon substrate with the three-coordinate bond state of nitrogen atoms and the silicon atoms being maintained.

    摘要翻译： 提供了一种方法：在硅衬底的表面上排列氮原子; 在氢气氛中进行热处理，使得存在于硅衬底表面上的氮原子和硅原子处于三配位键状态; 并且在硅衬底上形成具有氮原子的三配位键状态并保持硅原子的氧化硅膜。

    Method and equipment for manufacturing semiconductor device
    7.
    发明授权
    Method and equipment for manufacturing semiconductor device 失效
    制造半导体器件的方法和设备

    公开(公告)号：US06207591B1

    公开(公告)日：2001-03-27

    申请号：US09190444

    申请日：1998-11-13

    申请人： Nobutoshi Aoki ,  Ichiro Mizushima

    发明人： Nobutoshi Aoki ,  Ichiro Mizushima

    IPC分类号： H01L2126

    CPC分类号： H01L21/28185 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02312 ,  H01L21/28167 ,  H01L21/28211 ,  H01L21/31662 ,  H01L21/67115 ,  H01L21/823857

    摘要： A silicon wafer is heated from an initial pre-heating temperature (T0) up to a first annealing temperature (T1) by a rapid heating up step using an IR lamp. A first annealing is executed at the first annealing temperature (T1). Successively, while the silicon wafer is maintained at a second annealing temperature (T2) lower than the first annealing temperature (T1), a second annealing step is executed by a resistive heating furnace. A thermal oxidation can be executed as the second annealing step. To do so, an equipment for manufacturing a semiconductor device in the present invention is provided with: a heating device having an IR lamp and a resistive heater; an annealing tube having on a surface thereof a plurality of concave portions in such a way that each bottom approaches a central line; a resistive heater wrapped around this annealing tube; and an IR lamp movably inserted into and pulled out from the concave portion from the external. A IR lamp moving unit for moving the IR lamp is connected to the IR lamp. A wafer loader for mounting a plurality of wafers can be carried into and from the annealing tube. The first annealing step using the IR lamp at the rapid heating rate and successively the second annealing step using the resistive heater are performed on the plurality of wafers without performing a cooling step down to the room temperature. Accordingly, it is possible to effectively recover the damage induced by ion implantation and the like and also possible to suppress the enhanced diffusion of impurity resulting from the,damage to thereby improve the controllability of impurity distribution profile.

    摘要翻译： 通过使用IR灯的快速升温步骤将硅晶片从初始预热温度（T0）加热到第一退火温度（T1）。 在第一退火温度（T1）下执行第一退火。 接下来，当硅晶片保持在低于第一退火温度（T1）的第二退火温度（T2）时，通过电阻加热炉执行第二退火步骤。 作为第二退火工序，可以进行热氧化。 为此，本发明的半导体装置的制造装置具备：具有IR灯和电阻加热器的加热装置; 退火管在其表面上具有多个凹部，使得每个底部接近中心线; 围绕该退火管缠绕的电阻加热器; 以及从外部可移动地插入并从凹部中拉出的IR灯。 用于移动IR灯的IR灯移动单元连接到IR灯。 用于安装多个晶片的晶片加载器可以被携带到退火管中和从退火管中。 在多个晶片上执行以快速加热速率使用IR灯的第一退火步骤以及使用电阻加热器的第二退火步骤，而不进行至室温的冷却步骤。 因此，可以有效地回收由离子注入等引起的损伤，并且还可以抑制由于损伤引起的杂质的增强扩散，从而提高杂质分布特性的可控性。

    Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same
    9.
    发明授权
    Semiconductor integrated circuit including insulated gate field effect transistor and method of manufacturing the same 失效
    包括绝缘栅场效应晶体管的半导体集成电路及其制造方法

    公开(公告)号：US06744104B1

    公开(公告)日：2004-06-01

    申请号：US09440928

    申请日：1999-11-16

    申请人： Nobutoshi Aoki ,  Ichiro Mizushima ,  Kazuya Ohuchi

    发明人： Nobutoshi Aoki ,  Ichiro Mizushima ,  Kazuya Ohuchi

    IPC分类号： H01L2362

    CPC分类号： H01L21/2807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A gate electrode of an n-channel IGFET includes a first region composed of at least a first IV group element and a second IV group element which are different from each other, and a second region composed of the first IV group element. Similarly, a gate electrode of a p-channel IGFET includes first and second regions. For example, the first region is made of SiGe while the second region is made of Si. In both of the n-channel and P-channel IGFET, silicide electrodes are formed on the gate electrodes 4N and 4P through silicidation of at least parts of the second regions.

    摘要翻译： n沟道IGFET的栅电极包括由至少第一IV族元素和第二IV族元素组成的第一区域，第一IV族元素和第二IV族元素彼此不同，以及由第一IV族元素组成的第二区域。 类似地，p沟道IGFET的栅电极包括第一和第二区域。 例如，第一区域由SiGe制成，而第二区域由Si制成。 在n沟道和P沟道IGFET两者中，通过至少部分第二区域的硅化，在栅电极4N和4P上形成硅化物电极。

    Nonvolatile semiconductor memory device and method of fabricating the same
    10.
    发明授权
    Nonvolatile semiconductor memory device and method of fabricating the same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08624316B2

    公开(公告)日：2014-01-07

    申请号：US13227882

    申请日：2011-09-08

    申请人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

    发明人： Ichiro Mizushima ,  Yoshiaki Fukuzumi ,  Shinji Mori

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L27/11582 ,  H01L29/42352

    摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.

    摘要翻译： 根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱， 设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层， 面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。