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    Nonvolatile semiconductor memory device and manufacturing method for same
    1.
    发明授权
    Nonvolatile semiconductor memory device and manufacturing method for same 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08450713B2

    公开(公告)日：2013-05-28

    申请号：US12713223

    申请日：2010-02-26

    申请人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

    发明人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

    IPC分类号： H01L45/00 ,  H01L21/822

    CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616

    摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

    摘要翻译： 具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME 有权
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US20100219392A1

    公开(公告)日：2010-09-02

    申请号：US12713223

    申请日：2010-02-26

    申请人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

    发明人： Nobuyoshi Awaya ,  Yoshiji Ohta ,  Yoshiaki Tabuchi

    IPC分类号： H01L45/00 ,  H01L21/822

    CPC分类号： H01L27/249 ,  G11C13/0007 ,  G11C2013/0083 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/77 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2418 ,  H01L27/2436 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1616

    摘要： A three-dimensional memory cell array of memory cells with two terminals having a variable resistive element is formed such that: one ends of memory cells adjacent in Z direction are connected to one of middle selection lines extending in Z direction aligned in X and Y directions; the other ends of the memory cells located at the same point in Z direction are connected to one of third selection lines aligned in Z direction; a two-dimensional array where selection transistors are aligned in X and Y directions is adjacent to the memory cell array in Z direction; gates of selection transistors adjacent in X direction, drains of selection transistors adjacent in Y direction and sources of selection transistors are connected to same first selection line, second selection line, and different middle selection lines, respectively; and first, second and third selection lines are connected to X, Y and Z decoders, respectively.

    摘要翻译： 具有两个具有可变电阻元件的端子的存储单元的三维存储单元阵列被形成为：在Z方向上相邻的存储单元的一端连接到沿Z方向延伸的中间选择线之一，在X和Y方向上对齐 ; 位于Z方向相同点的存储单元的另一端连接到在Z方向上排列的第三选择线之一; 选择晶体管在X和Y方向上排列的二维阵列与Z方向上的存储单元阵列相邻; 在X方向上相邻的选择晶体管的栅极，在Y方向相邻的选择晶体管的漏极和选择晶体管的源极分别连接到相同的第一选择线，第二选择线和不同的中间选择线; 并且第一，第二和第三选择线分别连接到X，Y和Z解码器。

    Nonvolatile semiconductor memory device
    5.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08645795B2

    公开(公告)日：2014-02-04

    申请号：US13462846

    申请日：2012-05-03

    申请人： Kazuya Ishihara ,  Yoshiaki Tabuchi

    发明人： Kazuya Ishihara ,  Yoshiaki Tabuchi

    IPC分类号： G11C29/00

    CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2029/0411

    摘要： The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.

    摘要翻译： 本发明提供一种能够优化执行错误检测和校正处理的定时以缩短处理时间的非易失性半导体存储器件。 一旦输入/输出缓冲器向写入控制单元和ECC控制单元输出写入数据，就向存储单元阵列接收到写入请求，该存储单元阵列包括基于可变电阻器的电阻状态存储信息的可变电阻元件。 写入控制单元执行写入分割数据的数据写入处理，该分割数据是通过将写入数据划分成预定数量的数据而获得的。 ECC控制单元通过与数据写入处理并行地对写入数据或分割数据执行纠错码生成处理来生成第一纠错码。 写入控制单元执行将第一测试数据写入ECC组的代码写入处理。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20120297268A1

    公开(公告)日：2012-11-22

    申请号：US13462846

    申请日：2012-05-03

    申请人： Kazuya ISHIHARA ,  Yoshiaki Tabuchi

    发明人： Kazuya ISHIHARA ,  Yoshiaki Tabuchi

    IPC分类号： G11C29/04 ,  G06F11/16

    CPC分类号： G11C29/52 ,  G06F11/1048 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2029/0411

    摘要： The present invention provides a nonvolatile semiconductor memory device that can optimize a timing of performing an error detection and correction process to shorten a processing time. Upon receiving a write request to a memory cell array including a variable resistive element where information is stored based on a resistance state of a variable resistor, an input/output buffer outputs write data to a write control unit and an ECC control unit. The write control unit performs a data write process of writing divided data, obtained by dividing the write data into a predetermined number of data, to the databanks. The ECC control unit generates a first error correction code by performing an error correction code generation process to the write data or the divided data, in parallel with the data write process. The write control unit performs a code write process of writing first test data into an ECC bank.

    摘要翻译： 本发明提供一种能够优化执行错误检测和校正处理的定时以缩短处理时间的非易失性半导体存储器件。 一旦输入/输出缓冲器向写入控制单元和ECC控制单元输出写入数据，就向存储单元阵列接收到写入请求，该存储单元阵列包括基于可变电阻器的电阻状态存储信息的可变电阻元件。 写入控制单元执行写入分割数据的数据写入处理，该分割数据是通过将写入数据划分成预定数量的数据而获得的。 ECC控制单元通过与数据写入处理并行地对写入数据或分割数据执行纠错码生成处理来生成第一纠错码。 写入控制单元执行将第一测试数据写入ECC组的代码写入处理。