公开(公告)号：US20070162884A1

公开(公告)日：2007-07-12

申请号：US11705448

申请日：2007-02-13

申请人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

发明人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F21/75 ,  G06K19/07372 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

公开(公告)号：US20050050507A1

公开(公告)日：2005-03-03

申请号：US10914334

申请日：2004-08-10

申请人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

发明人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

IPC分类号： H01L21/3205 ,  G06F17/50 ,  G06F21/00 ,  G06K19/073 ,  H01L21/28 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/82 ,  H01L21/822 ,  H01L23/52 ,  H01L23/522 ,  H01L23/58 ,  H01L27/04 ,  H01L29/40 ,  H01L29/51

CPC分类号： G06F17/5077 ,  G06F21/75 ,  G06K19/07372 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the wires being on one of opposite sides, and the other ends of the wires being on the other one of the opposite sides, wherein: each of the one ends of the wires is point-symmetric to any of the other ends of the wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

摘要翻译： 本发明的基本单元包括构成90°的布线路径的多条线，所述线的一端位于相对的一侧，并且所述线的另一端位于相对的另一侧， 其中：所述导线的每一端相对于所述基本单元的区域的中心点对称到所述导线的任何另一端; 并且多条电线的路线不会彼此交叉。

公开(公告)号：US07376928B2

公开(公告)日：2008-05-20

申请号：US11705448

申请日：2007-02-13

申请人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

发明人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F21/75 ,  G06K19/07372 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

摘要翻译： 本发明的基本单元包括构成90°的布线路径的多条线，多条线的一端在相对的一侧上，多条线的另一端在另一条线上 相对侧，其中：所述多根线中的每一端相对于所述基本单元的区域的中心与所述多根金属丝的任何另一端点对称; 并且多条电线的路线不会彼此交叉。

公开(公告)号：US07194719B2

公开(公告)日：2007-03-20

申请号：US10914334

申请日：2004-08-10

申请人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

发明人： Noriaki Matsuno ,  Masato Tsunoda ,  Hirofumi Wada

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F21/75 ,  G06K19/07372 ,  H01L23/522 ,  H01L23/576 ,  H01L2924/0002 ,  H01L2924/00

摘要： A basic cell of the present invention comprises a plurality of wires which constitute a wiring route of 90°, one ends of the plurality of wires being on one of opposite sides, and the other ends of the plurality of wires being on the other one of the opposite sides, wherein: each of the one ends of the plurality of wires is point-symmetric to any of the other ends of the plurality of wires with respect to the center of the area of the basic cell; and routes of the plurality of wires do not cross one another.

摘要翻译： 本发明的基本单元包括构成90°的布线路径的多条线，多条线的一端在相对的一侧上，多条线的另一端在另一条线上 相对侧，其中：所述多根线中的每一端相对于所述基本单元的区域的中心与所述多根金属丝的任何另一端点对称; 并且多条电线的路线不会彼此交叉。

公开(公告)号：US20050280038A1

公开(公告)日：2005-12-22

申请号：US10520155

申请日：2003-07-14

申请人： Rie Itoh ,  Noriaki Matsuno ,  Masato Tsunoda

发明人： Rie Itoh ,  Noriaki Matsuno ,  Masato Tsunoda

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L27/10 ,  H01L29/74

CPC分类号： H01L23/576 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

摘要： A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.

摘要翻译： 半导体集成电路器件（10）由形成在该单元上的LSI功能单元（11）和屏蔽布线层（22）组成。 LSI功能单元（11）包括半导体衬底（12）和第一绝缘膜（13），并且半导体衬底（12）形成有包括例如MOS晶体管（14）的电路元件。 屏蔽布线层（22）由顺序堆叠在第二绝缘膜上的下屏蔽线（23），第三绝缘膜（24），上屏蔽线（25）和第四绝缘膜（26） 17）。 上下屏蔽线（23）和（25）的布置方向相互交叉。

公开(公告)号：US06998654B2

公开(公告)日：2006-02-14

申请号：US10520155

申请日：2003-07-14

申请人： Rie Itoh ,  Noriaki Matsuno ,  Masato Tsunoda

发明人： Rie Itoh ,  Noriaki Matsuno ,  Masato Tsunoda

IPC分类号： H01L27/10

CPC分类号： H01L23/576 ,  H01L23/5222 ,  H01L23/5225 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S257/922 ,  H01L2924/00

摘要： A semiconductor integrated circuit device (10) is composed of an LSI function unit (11) and a shield wiring layer (22) formed on the unit. The LSI function unit (11) includes a semiconductor substrate (12) and a first insulating film (13), and the semiconductor substrate (12) is formed with a circuit element including, for example, a MOS transistor (14). The shield wiring layer (22) is composed of a lower shield line (23), a third insulating film (24), an upper shield line (25), and a fourth insulating film (26) sequentially stacked above a second insulating film (17). The directions in which the lower and upper shield lines (23) and (25) are arranged intersect each other.

摘要翻译： 半导体集成电路器件（10）由形成在该单元上的LSI功能单元（11）和屏蔽布线层（22）组成。 LSI功能单元（11）包括半导体衬底（12）和第一绝缘膜（13），并且半导体衬底（12）形成有包括例如MOS晶体管（14）的电路元件。 屏蔽布线层（22）由顺序堆叠在第二绝缘膜上的下屏蔽线（23），第三绝缘膜（24），上屏蔽线（25）和第四绝缘膜（26） 17）。 上下屏蔽线（23）和（25）的布置方向相互交叉。

公开(公告)号：US07609046B2

公开(公告)日：2009-10-27

申请号：US12233853

申请日：2008-09-19

申请人： Hirofumi Wada ,  Atsuo Inoue ,  Noriaki Matsuno

发明人： Hirofumi Wada ,  Atsuo Inoue ,  Noriaki Matsuno

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147

摘要： An inverse temperature characteristic generating circuit decreases an output voltage Vout by a voltage VGS, and supplies the resultant voltage as a voltage VA to a temperature characteristic generating circuit. The temperature characteristic generating circuit includes a differential amplification circuit that receives a terminal voltage VAP between resistances R22 and R23 and an emitter voltage VAM of a bipolar transistor T21, and outputs a control signal VC. When the terminal voltages VAP and VAM are equal to each other, an operation of a circuit is stable. The temperature characteristic of the voltage VA during the stable operation, and the temperature characteristic of the voltage VGS are inverse to each other and therefore cancel each other, so that the constant voltage Vout independent of temperature is output. In addition, the output terminal is not connected via a resistance to a ground, so that low current consumption can be easily achieved.

摘要翻译： 逆温度特性发生电路通过电压VGS降低输出电压Vout，并将所得到的电压作为电压VA提供给温度特性产生电路。 温度特性发生电路包括差分放大电路，其接收电阻R22和R23之间的端子电压VAP和双极晶体管T21的发射极电压VAM，并输出控制信号VC。 当端子电压VAP和VAM彼此相等时，电路的操作是稳定的。 稳定运行时的电压VA的温度特性和电压VGS的温度特性彼此相反，因此彼此抵消，从而输出与温度无关的恒定电压Vout。 此外，输出端子不通过电阻连接到地，从而可以容易地实现低电流消耗。

公开(公告)号：US20090121700A1

公开(公告)日：2009-05-14

申请号：US12233853

申请日：2008-09-19

申请人： Hirofumi WADA ,  Atsuo Inoue ,  Noriaki Matsuno

发明人： Hirofumi WADA ,  Atsuo Inoue ,  Noriaki Matsuno

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147

摘要： An inverse temperature characteristic generating circuit decreases an output voltage Vout by a voltage VGS, and supplies the resultant voltage as a voltage VA to a temperature characteristic generating circuit. The temperature characteristic generating circuit includes a differential amplification circuit that receives a terminal voltage VAP between resistances R22 and R23 and an emitter voltage VAM of a bipolar transistor T21, and outputs a control signal VC. When the terminal voltages VAP and VAM are equal to each other, an operation of a circuit is stable. The temperature characteristic of the voltage VA during the stable operation, and the temperature characteristic of the voltage VGS are inverse to each other and therefore cancel each other, so that the constant voltage Vout independent of temperature is output. In addition, the output terminal is not connected via a resistance to a ground, so that low current consumption can be easily achieved.

摘要翻译： 逆温度特性发生电路通过电压VGS降低输出电压Vout，并将所得到的电压作为电压VA提供给温度特性产生电路。 温度特性发生电路包括差分放大电路，其接收电阻R22和R23之间的端子电压VAP和双极晶体管T21的发射极电压VAM，并输出控制信号VC。 当端子电压VAP和VAM彼此相等时，电路的操作是稳定的。 稳定运行时的电压VA的温度特性和电压VGS的温度特性彼此相反，因此彼此抵消，从而输出与温度无关的恒定电压Vout。 此外，输出端子不通过电阻连接到地，从而可以容易地实现低电流消耗。

公开(公告)号：US20110085625A1

公开(公告)日：2011-04-14

申请号：US12902679

申请日：2010-10-12

申请人： Tatsuya URAKAWA ,  Noriaki Matsuno

发明人： Tatsuya URAKAWA ,  Noriaki Matsuno

IPC分类号： H04L27/08 ,  H04B1/06

CPC分类号： H04B1/10 ,  H03G1/0088 ,  H03G3/3052

摘要： A receiver includes an automatic gain control (AGC) loop and a filter group that is arranged downstream of the AGC loop. The filter group includes an active filter. The receiver further includes a power difference detector and a switch circuit. The power difference detector detects a power difference between intermediate and output nodes of the filter group to detect presence of an interference wave that is different from a desired wave and that has a frequency near that of the desired wave. The switch circuit switches an operation to suppress a convergence power of the AGC loop when the power difference detector detects the interference wave.

摘要翻译： 接收机包括自动增益控制（AGC）环路和布置在AGC环路下游的滤波器组。 滤波器组包括有源滤波器。 接收器还包括功率差检测器和开关电路。 功率差检测器检测滤波器组的中间和输出节点之间的功率差异，以检测不同于期望波并且具有接近所需波的频率的干扰波的存在。 当功率差检测器检测到干扰波时，开关电路切换抑制AGC环路的会聚功率的操作。

公开(公告)号：US07768811B2

公开(公告)日：2010-08-03

申请号：US11854197

申请日：2007-09-12

申请人： Noriaki Matsuno ,  Atsuo Inoue

发明人： Noriaki Matsuno ,  Atsuo Inoue

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The ferroelectric memory apparatus stores data, and includes: a ferroelectric memory element; a temperature sensor which detects a temperature of the apparatus; a control unit that outputs a control signal indicating a voltage, the voltage increasing as the temperature detected by the temperature sensor decreases; and a voltage generating unit that generates the voltage indicated by the control signal outputted by the control unit, and to supply the generated voltage to the ferroelectric memory element. This provides a ferroelectric memory apparatus which can recover from effects of thermal stress suffered after shipment—i.e., reduction in the polarization amount needed for data retention as well as imprint degradation—using a relatively simple configuration.

摘要翻译： 铁电存储装置存储数据，并且包括：铁电存储元件; 检测装置的温度的温度传感器; 控制单元，其输出指示电压的控制信号，随着温度传感器检测到的温度而降低的电压增加; 以及电压产生单元，其产生由控制单元输出的控制信号所指示的电压，并将产生的电压提供给铁电存储元件。 这提供了一种铁电存储装置，其可以从出货后遭受的热应力的影响中恢复，即，使用相对简单的配置减少数据保持所需的极化量以及压痕退化。