公开(公告)号：US20100253182A1

公开(公告)日：2010-10-07

申请号：US12813550

申请日：2010-06-11

申请人： Norihiko TAKADA ,  Hayami Kudo

发明人： Norihiko TAKADA ,  Hayami Kudo

IPC分类号： H01L41/047 ,  H01L41/053 ,  B32B38/10 ,  H01L41/22

CPC分类号： H03H9/1092 ,  H03H9/02897 ,  H03H9/1071 ,  Y10T156/1052

摘要： A surface acoustic wave device causing less wear of a dicing blade and causing less drop in a dicing speed is manufactured from a mother laminate with high yield and high precision. The surface acoustic wave device is manufactured by dicing a piezoelectric wafer. The surface acoustic wave device includes a piezoelectric substrate resulting from dicing the piezoelectric wafer, IDT electrodes and pad electrodes located on a top surface of the piezoelectric substrate. A support layer having an opening opened to the IDT electrodes is provided. An outline edge of the support layer is inside an outline edge of the top surface of the piezoelectric substrate. A cover made of an insulating material is disposed on the support layer to close the opening of the support layer. In plan view, the outline edge of the cover is aligned with the outline edge of the piezoelectric substrate.

摘要翻译： 以高产率和高精度从母层压板制造引起切割刀片磨损较小并且切割速度降低较少的表面声波装置。 表面声波装置通过切割压电晶片来制造。 声表面波装置包括压电基片，其压电基片的顶表面上形成压电晶片，IDT电极和焊盘电极。 提供了具有向IDT电极开口的开口的支撑层。 支撑层的轮廓边缘在压电基板的顶表面的轮廓边缘的内侧。 由绝缘材料制成的盖子设置在支撑层上以封闭支撑层的开口。 在平面图中，盖的轮廓边缘与压电基板的轮廓边缘对齐。

公开(公告)号：US07944125B2

公开(公告)日：2011-05-17

申请号：US12813550

申请日：2010-06-11

申请人： Norihiko Takada ,  Hayami Kudo

发明人： Norihiko Takada ,  Hayami Kudo

IPC分类号： H01L41/04 ,  H03H9/25

CPC分类号： H03H9/1092 ,  H03H9/02897 ,  H03H9/1071 ,  Y10T156/1052

摘要： A surface acoustic wave device causing less wear of a dicing blade and causing less drop in a dicing speed is manufactured from a mother laminate with high yield and high precision. The surface acoustic wave device is manufactured by dicing a piezoelectric wafer. The surface acoustic wave device includes a piezoelectric substrate resulting from dicing the piezoelectric wafer, IDT electrodes and pad electrodes located on a top surface of the piezoelectric substrate. A support layer having an opening opened to the IDT electrodes is provided. An outline edge of the support layer is inside an outline edge of the top surface of the piezoelectric substrate. A cover made of an insulating material is disposed on the support layer to close the opening of the support layer. In plan view, the outline edge of the cover is aligned with the outline edge of the piezoelectric substrate.

摘要翻译： 以高产率和高精度从母层压板制造引起切割刀片磨损较小并且切割速度降低较少的表面声波装置。 表面声波装置通过切割压电晶片来制造。 声表面波装置包括压电基片，其压电基片的顶表面上形成压电晶片，IDT电极和焊盘电极。 提供了具有向IDT电极开口的开口的支撑层。 支撑层的轮廓边缘在压电基板的顶表面的轮廓边缘的内侧。 由绝缘材料制成的盖子设置在支撑层上以封闭支撑层的开口。 在平面图中，盖的轮廓边缘与压电基板的轮廓边缘对齐。

公开(公告)号：US08461940B2

公开(公告)日：2013-06-11

申请号：US12850725

申请日：2010-08-05

申请人： Norihiko Takada ,  Atsushi Kadoi ,  Hayami Kudo

发明人： Norihiko Takada ,  Atsushi Kadoi ,  Hayami Kudo

IPC分类号： H03H9/00 ,  H03H9/15 ,  H03H9/25

CPC分类号： H03H3/00 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/0558 ,  H01L2224/056 ,  H01L2224/05644 ,  H01L2224/16225 ,  H01L2924/16235 ,  H01L2924/181 ,  H03H9/0523 ,  H03H9/059 ,  H03H9/1042 ,  H03H9/105 ,  H03H9/1085 ,  H03H9/1092 ,  Y10T29/49005 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014

摘要： An elastic wave device has a structure that prevents flux from flowing into a hollow space of the device during mounting of the device using solder bumps. The elastic wave device includes a substrate, a vibrating portion located on a first main surface of the substrate, pads located on the first main surface of the substrate and electrically connected to electrodes of the vibrating portion, a supporting layer arranged on the first main surface of the substrate so as to enclose the vibrating portion, a sheet-shaped cover layer composed of resin including synthetic rubber and disposed on the supporting layer so as to form a hollow space around the periphery of the vibrating portion, a protective layer composed of resin having resistance to flux and disposed on a side of the cover layer remote from the supporting layer, via conductors extending through the protective layer, the cover layer, and the supporting layer and connected to the pads, and external electrodes including solder bumps, disposed at ends of the via conductors adjacent to the protective layer.

摘要翻译： 弹性波装置具有这样的结构，即在使用焊料凸块安装装置期间防止焊剂流入装置的中空空间。 弹性波装置包括基板，位于基板的第一主表面上的振动部分，位于基板的第一主表面上的焊盘，电连接到振动部分的电极，支撑层布置在第一主表面上 以包围振动部分的方式形成由包括合成橡胶的树脂构成的片状覆盖层，并设置在支撑层上，以在振动部分的周围形成中空空间，由树脂构成的保护层 具有抵抗磁通的能力并且设置在远离支撑层的覆盖层的一侧，通过延伸穿过保护层，覆盖层和支撑层并连接到焊盘的导体，以及包括焊料凸块的外部电极， 通孔导体的与保护层相邻的端部。

公开(公告)号：US20070069844A1

公开(公告)日：2007-03-29

申请号：US10556700

申请日：2004-11-17

申请人： Hayami Kudo ,  Masahiko Kawaguchi ,  Yasuhiro Nakata

发明人： Hayami Kudo ,  Masahiko Kawaguchi ,  Yasuhiro Nakata

IPC分类号： H01F27/02

CPC分类号： H01F17/0013 ,  H01F41/041 ,  H01F2017/002

摘要： A chip inductor in which excellent Q characteristic is realized while advantages in its small size and low profile are ensured, as well as a method for manufacturing the same, is provided. A chip inductor 1 is constructed by alternately laminating plural conductor patterns 31, 32, 33, and 34 and plural insulating layers 35, 36, 37, and 38 on and above a ceramic substrate 2, and connecting these plural conductor patterns 31, 32, 33, and 34 to each other in series in the lamination direction thereof so as to constitute a coil 30. Specifically, the number of turns of the lowermost-layer conductor pattern 31 disposed immediately on the ceramic substrate 2 is specified to be larger than the numbers of turns of the other plural conductor patterns 32, 33, and 34, and the numbers of turns of the other plural conductor patterns 32, 33, and 34 are specified to be substantially equal to each other. Preferably, the number of turns of the conductor pattern 31 is specified to be about 1.5 times the numbers of turns of the other plural conductor patterns 32, 33, and 34.

摘要翻译： 提供确保了其小尺寸和低外形优点的优异Q特性的片式电感器及其制造方法。 芯片电感器1是通过在陶瓷基板2上和之上交替层叠多个导体图案31,32,33,34以及多个绝缘层35,36,37,38并将这些多个导体图案31,32,32,38连接起来而构成的。 33和34彼此在层叠方向上串联以构成线圈30.具体地说，紧接在陶瓷基板2上设置的最下层导体图案31的匝数被规定为大于 其他多个导体图案32,33,34的匝数和其他多个导体图案32,33,34的匝数被规定为大致相等。 优选地，导体图案31的匝数被规定为其他多个导体图案32,33和34的匝数的约1.5倍。

公开(公告)号：US07460000B2

公开(公告)日：2008-12-02

申请号：US10556700

申请日：2004-11-17

申请人： Hayami Kudo ,  Masahiko Kawaguchi ,  Yasuhiro Nakata

发明人： Hayami Kudo ,  Masahiko Kawaguchi ,  Yasuhiro Nakata

IPC分类号： H01F5/00

CPC分类号： H01F17/0013 ,  H01F41/041 ,  H01F2017/002

摘要： A chip inductor is constructed by alternately laminating plural conductor patterns and plural insulating layers on and above a ceramic substrate, and connecting the plural conductor patterns to each other in series in a lamination direction thereof so as to constitute a coil. Specifically, the number of turns of the lowermost conductor pattern disposed directly on the ceramic substrate is larger than the number of turns of the other plural conductor patterns and the number of turns of the other plural conductor patterns are substantially equal to each other. Preferably, the number of turns of the lowermost conductor pattern is about 1.5 times the number of turns of the other plural conductor patterns.

摘要翻译： 芯片电感器通过在陶瓷基板上和上方交替层叠多个导体图案和多个绝缘层而构成，并且将多个导体图案沿层叠方向彼此串联连接以构成线圈。 具体而言，直接配置在陶瓷基板上的最下层导体图案的匝数大于其他多个导体图案的匝数，其他多个导体图案的匝数大致相等。 优选地，最下面的导体图案的匝数是其他多个导体图案的匝数的约1.5倍。

公开(公告)号：US09245680B2

公开(公告)日：2016-01-26

申请号：US13601889

申请日：2012-08-31

申请人： Miho Kitamura ,  Hayami Kudo ,  Atsushi Yamamoto ,  Akihiro Nakamura

发明人： Miho Kitamura ,  Hayami Kudo ,  Atsushi Yamamoto ,  Akihiro Nakamura

IPC分类号： H01F5/00 ,  H01F27/30 ,  H01F1/00 ,  H01F17/00 ,  H01F41/04

CPC分类号： H01F17/0013 ,  H01F41/04 ,  H01F41/046 ,  H01F2017/008 ,  Y10T29/49075

摘要： There is provided a common mode choke coil in which a non-magnetic layer and a second magnetic layer stacked on a first magnetic layer and two facing conductive coils are included in the non-magnetic layer, the non-magnetic layer is formed of sintered glass ceramics, the conductive coils and are formed of a conductor containing copper, and at least one of the first magnetic layer and the second magnetic layer is formed of a sintered ferrite material containing Fe2O3, Mn2O3, NiO, ZnO and CuO. The sintered ferrite material has an Fe2O3-reduced content of 25 to 47 mol % and a Mn2O3-reduced content of 1 to 7.5 mol %, or Fe2O3-reduced content of 35 to 45 mol % and a Mn2O3-reduced content of 7.5 to 10 mol %, and a CuO reduced content of 5 mol %.

摘要翻译： 提供了一种共模扼流线圈，其中堆叠在第一磁性层上的非磁性层和第二磁性层和两个面对的导电线圈包括在非磁性层中，非磁性层由烧结玻璃形成 陶瓷，导电线圈，由含有铜的导体形成，并且第一磁性层和第二磁性层中的至少一个由含有Fe 2 O 3，Mn 2 O 3，NiO，ZnO和CuO的烧结铁氧体材料形成。 烧结铁氧体材料的Fe 2 O 3还原含量为25〜47摩尔％，Mn2O3还原含量为1〜7.5摩尔％，Fe2O3还原含量为35〜45摩尔％，Mn2O3还原含量为7.5〜10 mol％，CuO还原含量为5mol％。

公开(公告)号：US08067879B2

公开(公告)日：2011-11-29

申请号：US12836595

申请日：2010-07-15

申请人： Hayami Kudo ,  Yuichi Takamine ,  Katsuhiro Ikada

发明人： Hayami Kudo ,  Yuichi Takamine ,  Katsuhiro Ikada

IPC分类号： H01L41/053 ,  H03H9/25

CPC分类号： H03H9/1092 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/13 ,  H03H9/059 ,  H01L2924/00014

摘要： A piezoelectric device includes a piezoelectric substrate, a conductive pattern which is provided on one main surface of the piezoelectric substrate and which includes an IDT electrode, a supporting layer which is arranged on the one main surface of the piezoelectric substrate so as to surround the periphery of an IDT-forming region in which the IDT electrode is provided and which has a thickness greater than that of the IDT electrode, and a cover layer which is arranged on the supporting layer and which covers the IDT-forming region. The supporting layer includes removed sections provided at a plurality of positions at least in a region close to the IDT-forming region, the removed sections being obtained by partially removing a portion of the supporting layer to be bonded to the one main surface of the piezoelectric substrate.

摘要翻译： 一种压电装置，包括压电基板，设置在压电基板的一个主表面上并具有IDT电极的导电图案，支撑层布置在压电基板的一个主表面上以围绕周边 的IDT形成区域，其中设置有IDT电极并且其厚度大于IDT电极的厚度;以及覆盖层，其被布置在支撑层上并覆盖IDT形成区域。 支撑层包括设置在至少在靠近IDT形成区域的区域中的多个位置处的去除部分，所述去除部分通过部分地去除要结合到压电体的一个主表面的支撑层的一部分而获得 基质。