公开(公告)号：US20120153988A1

公开(公告)日：2012-06-21

申请号：US13239877

申请日：2011-09-22

申请人： Noriyuki Tokuhiro ,  Kazumasa Kubotera ,  Yasutaka Kanayama

发明人： Noriyuki Tokuhiro ,  Kazumasa Kubotera ,  Yasutaka Kanayama

IPC分类号： H03K19/003

CPC分类号： H03K19/0005 ,  G06F2213/0038 ,  H03K19/018571 ,  H03K19/018585 ,  H04L25/0278

摘要： In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

摘要翻译： 在半导体器件中，选择器根据发送器或接收器的阻抗是否调整而选择不同的参考电压，并且使参考电压发生器产生所选择的参考电压。 参考电压发生器产生由选择器选择的参考电压，并将产生的参考电压施加到阻抗调节器。 阻抗调节器根据输入参考电压分别调整发射器的阻抗和接收器的阻抗。

公开(公告)号：US08547133B2

公开(公告)日：2013-10-01

申请号：US13239877

申请日：2011-09-22

申请人： Noriyuki Tokuhiro ,  Kazumasa Kubotera ,  Yasutaka Kanayama

发明人： Noriyuki Tokuhiro ,  Kazumasa Kubotera ,  Yasutaka Kanayama

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  G06F2213/0038 ,  H03K19/018571 ,  H03K19/018585 ,  H04L25/0278

摘要： In a semiconductor device, a selector selects a different reference voltage depending on whether the impedance of a transmitter or of a receiver is to be adjusted, and causes a reference voltage generator to generate the selected reference voltage. The reference voltage generator generates the reference voltage selected by the selector and applies the generated reference voltage to an impedance adjuster. The impedance adjuster adjusts the impedance of the transmitter and the impedance of the receiver, separately from each other, in accordance with the input reference voltage.

摘要翻译： 在半导体器件中，选择器根据发送器或接收器的阻抗是否调整而选择不同的参考电压，并且使参考电压发生器产生所选择的参考电压。 参考电压发生器产生由选择器选择的参考电压，并将产生的参考电压施加到阻抗调节器。 阻抗调节器根据输入参考电压分别调整发射器的阻抗和接收器的阻抗。

公开(公告)号：US08788780B2

公开(公告)日：2014-07-22

申请号：US13472575

申请日：2012-05-16

申请人： Noriyuki Tokuhiro ,  Noriyuki Takahashi ,  Shinya Aiso

发明人： Noriyuki Tokuhiro ,  Noriyuki Takahashi ,  Shinya Aiso

IPC分类号： G06F12/00 ,  G11C11/4076 ,  G11C7/22

CPC分类号： G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： A signal restoration circuit includes a storage configured to store input signals by disposing the input signals in an input order, the input signals being readable from the storage in the disposed order, and a storage controller configured to control delay time from an input of the input signal to an output in the storage based on delay information of the input signal.

摘要翻译： 信号恢复电路包括：存储器，被配置为通过以输入顺序布置输入信号来存储输入信号，所述输入信号以所述排列顺序从所述存储器读取;以及存储控制器，被配置为控制来自所述输入的输入的延迟时间 基于输入信号的延迟信息向存储器中的输出发送信号。

公开(公告)号：US07298192B2

公开(公告)日：2007-11-20

申请号：US11510721

申请日：2006-08-28

申请人： Noriyuki Tokuhiro

发明人： Noriyuki Tokuhiro

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A digital DLL device is provided which can reduce an error with respect to a target delay amount. The device provides a delay to an input clock signal so as to equally divide a clock cycle T thereof into N parts, and includes first variable delay sections and second variable delay sections, each of which is formed of an arbitrary number of unit delay buffers connected in series with one another. A phase comparison section makes a compare between the phase of the input clock signal and the phase of an output signal which is the input signal having been delayed while passing through all the first and second variable delay sections, and outputs a result of the comparison. A delay control section calculates a total number of unit delay buffers S required based on the phase comparison result, sets a quotient Q of S divided by N to be the number of unit delay buffers for each of the first variable delay sections, and allocates a remainder R of S divided by N to the second variable delay sections, respectively.

摘要翻译： 提供一种数字DLL设备，其可以减少相对于目标延迟量的错误。 该装置向输入时钟信号提供延迟，以便将其时钟周期T均等地划分为N个部分，并且包括第一可变延迟部分和第二可变延迟部分，每个可变延迟部分和第二可变延迟部分由连接的任意数量的单位延迟缓冲器 相互串联。 相位比较部分比较输入时钟信号的相位和输入信号的相位，该输出信号是通过所有第一和第二可变延迟部分时被延迟的输入信号，并输出比较结果。 延迟控制部分根据相位比较结果计算所需的单位延迟缓冲器S的总数，将S除以N的商Q设定为每个第一可变延迟部分的单位延迟缓冲器的数量，并且分配 S的余数R除以N分别与第二可变延迟部分。

公开(公告)号：US07154981B2

公开(公告)日：2006-12-26

申请号：US10982778

申请日：2004-11-08

申请人： Noriyuki Tokuhiro ,  Kunihiro Itoh

发明人： Noriyuki Tokuhiro ,  Kunihiro Itoh

IPC分类号： H03K17/16

CPC分类号： H03K19/0005 ,  H04L25/0298

摘要： A termination circuit for terminating a transmission line comprises a resistance unit which is formed by connecting a P-channel type MOS transistor and an N-channel type MOS transistor in parallel, and Thevenin termination is formed by providing this resistance unit between the transmission line and a power supply line and between the transmission line and a ground line.

摘要翻译： 用于终止传输线的终端电路包括通过并联连接P沟道型MOS晶体管和N沟道型MOS晶体管而形成的电阻单元，并且通过在传输线和 电源线和传输线与接地线之间。

公开(公告)号：US08020022B2

公开(公告)日：2011-09-13

申请号：US12209740

申请日：2008-09-12

申请人： Noriyuki Tokuhiro

发明人： Noriyuki Tokuhiro

IPC分类号： G06F13/42

CPC分类号： G11C7/1078 ,  G06F13/1689 ,  G11C7/10 ,  G11C7/1093

摘要： A memory control circuit has a write leveling function and controls read/write operations by supplying a clock signal to a plurality of memories through a clock signal line which is wired to the plurality of memories through daisy chain connection. For each of the plurality of memories, a first variable delay unit delays, in a write operation, a data strobe signal output to the memory by a first delay time that is set by utilizing the write leveling function and a second variable delay unit delays, in a read operation, a data signal input from the memory by a second delay time that is set based on the first delay time.

摘要翻译： 存储器控制电路具有写调平功能，并且通过通过菊花链连接连接到多个存储器的时钟信号线向多个存储器提供时钟信号来控制读/写操作。 对于多个存储器中的每一个，第一可变延迟单元在写入操作中将通过利用写入调平功能设置的第一延迟时间和第二可变延迟单元延迟输出到存储器的数据选通信号延迟， 在读取操作中，从存储器输入基于第一延迟时间设置的第二延迟时间的数据信号。

公开(公告)号：US07102553B2

公开(公告)日：2006-09-05

申请号：US11202351

申请日：2005-08-10

申请人： Noriyuki Tokuhiro

发明人： Noriyuki Tokuhiro

IPC分类号： H03M9/00

CPC分类号： H04L25/45 ,  H03M9/00 ,  H04L25/4908

摘要： A signal transmission method and a signal transmission device capable of easily transmitting a signal with a small number of signal lines. A data signal of time slot count N+α with bit count N is longitudinal-lateral converted into a data signal of time slot count N with bit count N+α. so as to create a null time α and a control signal is inserted into the null time α, thereby converting the parallel signal containing the data signal and the control signal into a serial signal for transmission.

公开(公告)号：US08723569B2

公开(公告)日：2014-05-13

申请号：US13493421

申请日：2012-06-11

申请人： Noriyuki Tokuhiro

发明人： Noriyuki Tokuhiro

IPC分类号： H03L7/06

CPC分类号： G11C7/1066 ,  G06F13/1689 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0037

摘要： A signal receiving circuit includes a phase detection unit and a delay control unit. The phase detection unit detects a phase difference between a received signal and a clock signal. The delay control unit receives the phase difference, delays a phase of the received signal in a range not exceeding a delay amount determined by using a predetermined phase difference as a unit, and changes, when the phase difference exceeds the predetermined phase difference, a delay amount of the received signal by using the predetermined phase difference as a unit.

摘要翻译： 信号接收电路包括相位检测单元和延迟控制单元。 相位检测单元检测接收信号和时钟信号之间的相位差。 延迟控制单元接收相位差，在不超过以预定相位差确定的延迟量的范围内将接收信号的相位延迟为一个单位，并且当相位差超过预定相位差时改变延迟 通过使用预定相位差作为一个单位的接收信号量。

公开(公告)号：US20060022713A1

公开(公告)日：2006-02-02

申请号：US10986154

申请日：2004-11-12

申请人： Noriyuki Tokuhiro ,  Kunihiro Itoh

发明人： Noriyuki Tokuhiro ,  Kunihiro Itoh

IPC分类号： H03K19/094

CPC分类号： H03K19/0005 ,  H03K19/018585

摘要： A driver circuit for driving a device or circuit disposed after it comprises a plurality of driving transistors connected in parallel, a selection unit for selecting one or more groups from a plurality of groups to each of which driving transistors having a power base of two with the same polarity belong and in which the number of driving transistors belonging to each group is different and a driving unit for driving driving transistors belonging to the group selected by the selection unit.

摘要翻译： 一种用于驱动设置在其上的器件或电路的驱动器电路，其包括并联连接的多个驱动晶体管，用于从多个组中选择一个或多个组的选择单元，其中驱动晶体管的功率基数为2， 属于每个组的驱动晶体管的数量不同的驱动单元和属于由选择单元选择的组的驱动晶体管的驱动单元相同。

公开(公告)号：US20060022702A1

公开(公告)日：2006-02-02

申请号：US10989461

申请日：2004-11-17

申请人： Noriyuki Tokuhiro ,  Kunihiro Itoh

发明人： Noriyuki Tokuhiro ,  Kunihiro Itoh

IPC分类号： H03K19/003

CPC分类号： H03K19/018592 ,  H03K19/018585 ,  H04L25/0278

摘要： An interface circuit which is connected to a function unit such as a memory reduces the number of structural elements by using structural elements in common, and also realizes a plurality of different function circuits. The interface circuit connected with the function unit uses the structural elements for a plurality of circuits in common, and obtains necessary functions by controlling the structural elements. The interface circuit has first and second electronic devices such as FETs connected in series, and an external terminal, formed at an intermediate connected portion between the first electronic device and the second electronic device, to which the function unit is connected, and constitutes a function circuit part having different functions by controlling the first electronic device and the second electronic device.

摘要翻译： 连接到诸如存储器的功能单元的接口电路通过共同使用结构元件来减少结构元件的数量，并且还实现多个不同的功能电路。 与功能单元连接的接口电路共同地使用多个电路的结构元件，并且通过控制结构元件来获得必要的功能。 接口电路具有串联连接的诸如FET的第一和第二电子器件，以及形成在第一电子器件与第二电子器件之间的中间连接部分处的功能单元连接的外部端子，并且构成功能 电路部件通过控制第一电子设备和第二电子设备而具有不同的功能。