-
公开(公告)号：US10666141B2
公开(公告)日：2020-05-26
申请号：US16039359
申请日：2018-07-19
发明人： Cheng-Chih Wang
摘要： A control device includes a first switch, a second switch, a switching circuit, a first circuit and a second circuit. The control device is selectively switched to a first mode or a second mode corresponding to an operating current and an operating state of a predetermined circuit. During the first mode, an output signal of the first circuit is transmitted to a control end of the first switch through the switching circuit, and the first circuit and the first switch form a low drop-out regulator. During the second mode, a plurality of driving signals of the second circuit are transmitted to the control end of the first switch and a control end of the second switch through the switching circuit, and the first switch, the second switch and an impedance circuit form a switching voltage converter.
-
公开(公告)号：US10551862B2
公开(公告)日：2020-02-04
申请号：US16145205
申请日：2018-09-28
发明人： Cheng-Chih Wang
摘要： A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.
-
公开(公告)号：US20190138043A1
公开(公告)日：2019-05-09
申请号：US16145205
申请日：2018-09-28
发明人： Cheng-Chih Wang
摘要： A system on chip (SOC) is provided. The SOC includes a system core logic, a voltage regulator, a clock generator and a system balance circuit. The voltage regulator provides an operating voltage to the system core logic and receives a current setting signal to set the voltage regulator to a low current mode or a high current mode. The clock generator provides a reference clock signal. The system balance circuit receives the reference clock signal to provide the current setting signal to the voltage regulator and provides the system clock signal to the system core logic, wherein the current setting signal is used to set the voltage regulator to the high current mode before the system clock signal is enabled, and set the voltage regulator to the low current mode after the system clock signal is enabled.
-
公开(公告)号：US20190028028A1
公开(公告)日：2019-01-24
申请号：US16039359
申请日：2018-07-19
发明人： Cheng-Chih Wang
摘要： A control device and a power conversion circuit thereof are provided. The control device includes a first switch, a second switch, a switching circuit, a first circuit and a second circuit. The control device is selectively switched to a first mode or a second mode corresponding to an operating current and an operating state of a predetermined circuit. During the first mode, an output signal of the first circuit is transmitted to a control end of the first switch through the switching circuit, and the first circuit and the first switch form a low drop-out regulator. During the second mode, a plurality of driving signals of the second circuit are transmitted to the control end of the first switch and a control end of the second switch through the switching circuit, and the first switch, the second switch and an impedance circuit form a switching voltage converter.
-
公开(公告)号：US20180210540A1
公开(公告)日：2018-07-26
申请号：US15871022
申请日：2018-01-14
发明人： Cheng-Chih Wang , Hsi-Jung Tsai
CPC分类号： G06F1/3296 , G05F1/575 , G06F3/0625 , G11C5/147 , G11C7/24 , G11C13/0038 , G11C13/0069 , G11C16/10 , G11C16/30
摘要： A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.
-
公开(公告)号：US20170229177A1
公开(公告)日：2017-08-10
申请号：US15414643
申请日：2017-01-25
发明人： Cheng-Chih Wang
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/004 , G11C13/0069 , G11C14/009 , G11C2013/0073
摘要： A non-volatile memory (NVM) device includes a logic memory circuit, a NVM element, a writing circuit and a reading circuit. The input terminal of the writing circuit and the output terminal of the reading circuit are coupled to the output terminal of the logic memory circuit. The first output terminal of the writing circuit and the first input terminal of the reading circuit are coupled to the first terminal of the NVM element. The second output terminal of the writing circuit and the second input terminal of the reading circuit are coupled to the second terminal of the NVM element. During a writing period, the writing circuit writes the stored data of the logic memory circuit into the NVM element. During a reading period, the reading circuit restores the data of the NVM element to the output terminal of the logic memory circuit.
-
公开(公告)号：US20170026045A1
公开(公告)日：2017-01-26
申请号：US15135544
申请日：2016-04-21
发明人： Cheng-Chih Wang , Hsi-Jung Tsai
IPC分类号： H03K19/177 , H03K19/00
CPC分类号： H03K19/17776 , H03K19/0013 , H03K19/1776
摘要： A function programmable circuit and an operation method thereof are provided. The function programmable circuit includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is capable of being configured to execute a first function and work with the MCU in a first period, while the FPGA is being programmed a second function by the MCU in the same first period. The FPGA is controlled by a function switch pulse output from the MCU to terminate the first period, and switched from the first function to the second function, and then executes the second function and works with the MCU in a second period.
摘要翻译： 提供了一种功能可编程电路及其操作方法。 功能可编程电路包括微控制器单元（MCU）和现场可编程门阵列（FPGA）。 FPGA耦合到MCU，并且能够被配置为在第一时间段内执行第一个功能并与MCU一起工作，而FPGA在同一个第一时间段内被MCU编程为第二个功能。 FPGA由MCU的功能开关脉冲输出控制，终止第一个周期，从第一个功能切换到第二个功能，然后执行第二个功能，并在第二个时间内与MCU一起使用。
-
公开(公告)号：US11062779B2
公开(公告)日：2021-07-13
申请号：US16712332
申请日：2019-12-12
发明人： Cheng-Chih Wang
摘要： A data processing system includes a memory device, a predetermined voltage generating circuit and a reference voltage generating circuit. The memory device stores system data and operates based on a system high voltage. The predetermined voltage generating circuit is coupled to the memory device and generates a predetermined voltage having a target voltage level according to a reference voltage. The target voltage level is the voltage level required for performing a write operation or an erase operation of the memory device. The reference voltage generating circuit generates the reference voltage. A voltage generator of the reference voltage generating circuit is enabled or disabled in response to a write protection signal, so as to selectively output the reference voltage. When the voltage generator is disabled, the reference voltage will not be output and the predetermined voltage having a target voltage level will accordingly not be generated.
-
公开(公告)号：US10432196B2
公开(公告)日：2019-10-01
申请号：US15627459
申请日：2017-06-20
发明人： Cheng-Chih Wang
IPC分类号： H03K19/00 , H03K19/177 , H03K17/16
摘要： A communication device, a communication system and an operation method thereof are provided. The communication device includes a micro-controller unit (MCU) and a field programmable gate array (FPGA). The FPGA is coupled to the MCU, and is configured to execute a first communication protocol to work with the MCU so as to communicate with another communication device in a first period, and meanwhile the FPGA is programmed with a second communication protocol by the MCU in the same first period. The FPGA is controlled by a switch pulse output from the MCU to terminate the first period, and switched from the first communication protocol to the second communication protocol, and then executes the second communication protocol to work with the MCU so as to communicate with the another communication device in a second period.
-
公开(公告)号：US10275017B2
公开(公告)日：2019-04-30
申请号：US15871022
申请日：2018-01-14
发明人： Cheng-Chih Wang , Hsi-Jung Tsai
IPC分类号： G06F1/32 , G05F1/575 , G11C16/10 , G11C16/30 , G11C5/14 , G06F3/06 , G06F1/3296 , G11C7/24 , G11C13/00
摘要： A power circuit and a memory device using the same are provided. The power circuit is used for providing an operating voltage to a memory array, and includes a voltage regulator circuit and a voltage feedback circuit. The voltage regulator circuit receives a system voltage to provide the operating voltage. The voltage feedback circuit is coupled to the voltage regulator circuit to receive the operating voltage, and receives a data locking voltage, wherein the voltage feedback circuit has a non-volatile memory element which is set or reset in response to the data locking voltage. The voltage feedback circuit is set or reset based on the non-volatile memory element to provide a feedback voltage to the voltage regulator circuit, so as to set an output level of the operating voltage.
-
-
-
-
-
-
-
-
-
搜索结果
49 条记录 (耗时 0.022 秒)
