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公开(公告)号：US20130283129A1
公开(公告)日：2013-10-24
申请号：US13917773
申请日：2013-06-14
发明人： Franz Michael Schuette , Lutz Filor
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G06F11/0727 , G06F11/0751 , G11C29/52
摘要： A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.
摘要翻译： 一种固态大容量存储装置和方法，用于在达到写入耐力限制之前操作存储装置以预测其至少一个存储器件的故障。 该方法包括将存储器件的至少第一存储块分配为作为数据存储被排除的磨损指示符，使用用于数据存储的存储器件的至少一组存储器块的页面，将数据写入和擦除 在程序/擦除（P / E）循环中来自该组的每个存储器块的数据，对该组存储器块执行磨损均衡，对磨损指示器进行比该组存储器块更多的P / E周期，执行完整性检查 磨损指示器并监视其误码率，如果误码率增加，则采取纠正措施。
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公开(公告)号：US20130262960A1
公开(公告)日：2013-10-03
申请号：US13901827
申请日：2013-05-24
发明人： Franz Michael Schuette , Lutz Filor
IPC分类号： G11C29/52
CPC分类号： G11C29/00 , G06F11/0727 , G06F11/0751 , G11C29/52
摘要： A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.
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公开(公告)号：US20130223166A1
公开(公告)日：2013-08-29
申请号：US13775916
申请日：2013-02-25
CPC分类号： G11C7/00 , B82Y10/00 , B82Y99/00 , G11C13/025 , G11C2213/35 , H01L21/02107 , H01L29/1606 , H01L29/685
摘要： Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell
摘要翻译： 内存技术适用于以二进制格式存储数据。 这种技术包括具有存储单元的半导体存储器件，每个存储单元具有衬底和至少三个石墨烯层，其被定向成限定设置在平面中的石墨烯堆叠。 每个存储单元的石墨烯堆叠被连接到位线和接地连接，使得导电路径被限定在石墨烯叠层的平面中。 在存储器单元的编程期间改变每个存储单元的石墨烯堆叠的面内导电性，以限定存储在存储单元中的位的二进制值
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公开(公告)号：US08995137B2
公开(公告)日：2015-03-31
申请号：US13866098
申请日：2013-04-19
CPC分类号： G06F13/4081 , G06F3/0626 , G06F3/0658 , G06F3/0683
摘要： A modular mass storage system and method that enables cableless mounting of ATA and/or similar high speed interface-based mass storage devices in a computer system. The system includes a printed circuit board, a system expansion slot interface on the printed circuit board and comprising power and data pins, a host bus controller on the printed circuit board and electrically connected to the system expansion slot interface, docking connectors connected with the host bus controller to receive power and exchange data therewith and adapted to electrically couple with industry-standard non-volatile memory devices without cabling therebetween, and features on the printed circuit board for securing the memory devices thereto once coupled to the docking connectors.
摘要翻译： 一种模块化大容量存储系统和方法，其能够在计算机系统中无线地安装ATA和/或类似的基于高速接口的大容量存储设备。 该系统包括印刷电路板，印刷电路板上的系统扩展槽接口，并且包括电源和数据引脚，印刷电路板上的主机总线控制器和电连接到系统扩展槽接口，与主机连接的对接连接器 总线控制器接收电力并与其交换数据，并且适于与工业标准非易失性存储器件电耦合，而无需在其间进行电缆连接，以及印刷电路板上的特征，用于将存储器件固定到其上，一旦耦合到对接连接器。
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5.发明申请INTEGRATED STORAGE/PROCESSING DEVICES, SYSTEMS AND METHODS FOR PERFORMING BIG DATA ANALYTICS 有权用于执行大数据分析的集成存储/处理设备，系统和方法公开(公告)号：US20140129753A1
公开(公告)日：2014-05-08
申请号：US13669727
申请日：2012-11-06
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , G06F2213/0026
摘要： Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.
摘要翻译： 提供包含形成大型非易失性存储器阵列的非易失性存储器件的集成存储/处理系统和为通用（GPGPU）计算配置的图形处理单元（GPU），从而进行大数据分析的体系结构和方法。 非易失性存储器阵列与GPU直接功能耦合（本地），并且可选地安装在与GPU相同的板（板上）上。
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6.发明授权Integrated storage/processing devices, systems and methods for performing big data analytics 有权用于执行大数据分析的集成存储/处理设备，系统和方法公开(公告)号：US08996781B2
公开(公告)日：2015-03-31
申请号：US13669727
申请日：2012-11-06
IPC分类号： G06F13/40
CPC分类号： G06F13/4068 , G06F2213/0026
摘要： Architectures and methods for performing big data analytics by providing an integrated storage/processing system containing non-volatile memory devices that form a large, non-volatile memory array and a graphics processing unit (GPU) configured for general purpose (GPGPU) computing. The non-volatile memory array is directly functionally coupled (local) with the GPU and optionally mounted on the same board (on-board) as the GPU.
摘要翻译： 提供包含形成大型非易失性存储器阵列的非易失性存储器件的集成存储/处理系统和为通用（GPGPU）计算配置的图形处理单元（GPU），从而进行大数据分析的架构和方法。 非易失性存储器阵列与GPU直接功能耦合（本地），并且可选地安装在与GPU相同的板（板上）上。
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公开(公告)号：US20140136766A1
公开(公告)日：2014-05-15
申请号：US14079192
申请日：2013-11-13
CPC分类号： G06F3/0679 , G06F3/0626 , G06F3/0656 , G06F3/0658 , G06F3/0676 , G11B20/10527
摘要： A solid-state mass storage device adapted to be used as a cache for an hard disk drive that utilizes a more efficient logical data management method relative to conventional systems. The storage device includes a circuit board, a memory controller, at least one non-volatile memory device, and at least two data interfaces. The storage device is coupled to a host computer system and configured to operate as a cache for at least one hard disk drive. The storage device is interposed between the host computer system and the at least one hard disk drive. Both the storage device and the at least one hard disk drive are coupled to the host computer system through a single connection and configured to operate in a daisy chain configuration.
摘要翻译： 一种固态海量存储装置，适用于相对于常规系统利用更有效的逻辑数据管理方法的硬盘驱动器的高速缓存。 存储装置包括电路板，存储器控制器，至少一个非易失性存储器件以及至少两个数据接口。 存储设备耦合到主计算机系统并且被配置为作为至少一个硬盘驱动器的高速缓存操作。 存储设备插入在主计算机系统和至少一个硬盘驱动器之间。 存储设备和至少一个硬盘驱动器通过单个连接耦合到主计算机系统，并被配置为以菊花链配置操作。
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8.发明申请APPARATUS, METHODS AND ARCHITECTURE TO INCREASE WRITE PERFORMANCE AND ENDURANCE OF NON-VOLATILE SOLID STATE MEMORY COMPONENTS 有权增加非易失性固态存储器组件的写性能和耐用性的装置，方法和架构公开(公告)号：US20130205076A1
公开(公告)日：2013-08-08
申请号：US13758346
申请日：2013-02-04
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0871 , G06F12/122 , G06F2212/214 , G06F2212/222 , G06F2212/225
摘要： A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.
摘要翻译： 一种用于与主机系统一起使用的固体大容量存储装置，以及增加其定义第一非易失性存储器空间的非易失性存储器组件的耐久性的方法。 大容量存储设备还具有第二非易失性存储器空间，其包含比第一非易失性存储器空间的存储器组件具有更高的写入耐久性的至少一个非易失性存储器组件。 第二非易失性存储器空间用作用于主机向第一非易失性存储器空间写入的低通滤波器，以最小化对第一非易失性存储器空间的读取访问。 使用更改计数器来管理第二非易失性存储器空间的内容。
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9.发明授权Apparatus, methods and architecture to increase write performance and endurance of non-volatile solid state memory components 有权提高非易失性固态存储器组件的写入性能和耐久性的装置，方法和架构公开(公告)号：US09081665B2
公开(公告)日：2015-07-14
申请号：US13758346
申请日：2013-02-04
CPC分类号： G06F12/0246 , G06F12/0871 , G06F12/122 , G06F2212/214 , G06F2212/222 , G06F2212/225
摘要： A solid-state mass storage device for use with host computer systems, and methods of increasing the endurance of non-volatile memory components thereof that define a first non-volatile memory space. The mass storage device further has a second non-volatile memory space containing at least one non-volatile memory component having a higher write endurance than the memory components of the first non-volatile memory space. The second non-volatile memory space functions as a low-pass filter for host writes to the first non-volatile memory space to minimize read accesses to the first non-volatile memory space. Contents of the second non-volatile memory space are managed using a change counter.
摘要翻译： 一种用于与主机系统一起使用的固体大容量存储装置，以及增加其定义第一非易失性存储器空间的非易失性存储器组件的耐久性的方法。 大容量存储设备还具有第二非易失性存储器空间，其包含比第一非易失性存储器空间的存储器组件具有更高的写入耐久性的至少一个非易失性存储器组件。 第二非易失性存储器空间用作用于主机向第一非易失性存储器空间写入的低通滤波器，以最小化对第一非易失性存储器空间的读取访问。 使用更改计数器来管理第二非易失性存储器空间的内容。
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公开(公告)号：US08964491B2
公开(公告)日：2015-02-24
申请号：US13775916
申请日：2013-02-25
CPC分类号： G11C7/00 , B82Y10/00 , B82Y99/00 , G11C13/025 , G11C2213/35 , H01L21/02107 , H01L29/1606 , H01L29/685
摘要： Memory technology adapted to store data in a binary format. Such technology includes a semiconductor memory device having memory cells, each having a substrate and at least three graphene layers that are oriented to define a graphene stack disposed in a plane. The graphene stack of each memory cell is connected to a bit line and to a ground connection so that a conductive path is defined in the plane of the graphene stack. The in-plane conductivity of the graphene stack of each memory cell is altered during programming of the memory cell to define a binary value of bits stored in the memory cell.
摘要翻译： 内存技术适用于以二进制格式存储数据。 这种技术包括具有存储单元的半导体存储器件，每个存储单元具有衬底和至少三个石墨烯层，其被定向成限定设置在平面中的石墨烯堆叠。 每个存储单元的石墨烯堆叠被连接到位线和接地连接，使得导电路径被限定在石墨烯叠层的平面中。 在存储器单元的编程期间改变每个存储单元的石墨烯层的面内电导率，以限定存储在存储单元中的位的二进制值。
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