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公开(公告)号:US20240057966A1
公开(公告)日:2024-02-22
申请号:US18230209
申请日:2023-08-04
申请人: ONKYO CORPORATION
IPC分类号: A61B7/04
CPC分类号: A61B7/04
摘要: An electronic device comprising: a circuit; an enclosure which stores the circuit; and an earth plate which is provided at the enclosure and exposes to an outside.
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公开(公告)号:US20190341890A1
公开(公告)日:2019-11-07
申请号:US16388529
申请日:2019-04-18
申请人: Onkyo Corporation
发明人: Makoto YOSHIDA
摘要: An amplification device comprising: a push pull circuit which amplifies an input signal; a diamond buffer circuit to which the signal which is amplified by the push pull circuit is input; and a current mirror circuit which is connected to a power supply and the diamond buffer circuit and is connected to a retraction current terminal of the push pull circuit.
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公开(公告)号:US20180177040A1
公开(公告)日:2018-06-21
申请号:US15840598
申请日:2017-12-13
申请人: Onkyo Corporation
发明人: Makoto YOSHIDA
CPC分类号: H05K1/115 , H05K1/0215 , H05K1/0216 , H05K1/0225 , H05K1/0259 , H05K9/0039 , H05K9/006 , H05K2201/093 , H05K2201/09327 , H05K2201/09354
摘要: A multilayer substrate includes plural layers of circuit patterns. Each circuit pattern includes a ground conductor surrounding a wiring region provided with a conductive wiring pattern. Each ground conductor includes a slit connecting between the outside of the multilayer substrate and the wiring region. In the multilayer substrate, the slit of the ground conductor provided at one of adjacent two layers of the circuit patterns and the slit of the ground conductor provided at the other circuit pattern are formed at positions not overlapping with each other. That is, these slits are formed at such positions that a view in an upper-to-lower direction is blocked. The shape of the slit of each ground conductor is in such a shape that a view from an end side of the multilayer substrate to a wiring region side is blocked.
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公开(公告)号:US20170064455A1
公开(公告)日:2017-03-02
申请号:US15238634
申请日:2016-08-16
申请人: Onkyo Corporation
发明人: Kei ASAO , Tsuyoshi KAWAGUCHI , Makoto YOSHIDA , Takanori SHIOZAKI , Yoshinori NAKANISHI , Hiroyuki ASAHARA , Norimasa KITAGAWA
CPC分类号: H04R5/033 , H03F3/187 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03F2203/7227 , H03M1/66 , H04R5/04
摘要: To reduce signal output and wiring to a D/A converter (DAC).A DAP 1 comprises a DAC 7 that D/A-converts LR 2 channels digital audio data into LR 2 channels analog audio data, an amplification circuit 9 that amplifies the LR 2 channels analog audio data that the DAC 7 D/A-converts, a DAC 8 that D/A-converts the LR 2 channels digital audio data into the LR 2 channels analog audio data, and an amplification circuit 10 that amplifies inverted LR 2 channels analog audio data that the LR 2 channels analog audio data that the DAC 8 D/A-converts is inverted.
摘要翻译: DAP1包括将LR2将数字音频数据D / A转换成LR2声道模拟音频数据的DAC7,放大电路9,放大电路9放大DAC7 D / A转换的模拟音频数据, 将LR2声道数字音频数据进行D / A转换为LR2声道的模拟音频数据的DAC8以及放大反向LR2声道的模拟音频数据的放大电路10,LR 2通道模拟音频数据为DAC 8个D / A转换器被反转。
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公开(公告)号:US20170063320A1
公开(公告)日:2017-03-02
申请号:US15238644
申请日:2016-08-16
申请人: Onkyo Corporation
发明人: Kei ASAO , Tsuyoshi KAWAGUCHI , Makoto YOSHIDA , Takanori SHIOZAKI , Yoshinori NAKANISHI , Hiroyuki ASAHARA , Norimasa KITAGAWA
CPC分类号: H03G3/341 , H03F1/26 , H03F3/183 , H03F3/187 , H03F3/45475 , H03F3/72 , H03F2200/03 , H03G3/348 , H03M1/66 , H04R5/04
摘要: To realize active control ground that sets inverted output of an amplification circuit to ground with simple configuration.A DAP 1 comprises a positive side DAC 7 that D/A-converts digital audio data into analog audio data, a positive side amplification circuit 9 that amplifies the analog audio data that the DAC 7 D/A-converts, a negative side DAC 8 that D/A-converts the digital audio data into the analog audio data, and a negative side amplification circuit 10 that amplifies the analog audio data that the DAC 8 D/A-converts, and a CPU 2. The CPU 2 mutes the DAC 8 in case of an ACG mode that sets output of the amplification circuit 10 to ground.
摘要翻译: DAP1包括将数字音频数据D / A转换成模拟音频数据的正侧DAC7,放大DAC7 D / A转换的模拟音频数据的正侧放大电路9,负侧DAC 8 将数字音频数据D / A转换为模拟音频数据,以及放大DAC 8 D / A转换的模拟音频数据的负侧放大电路10和CPU 2. CPU 2使DAC静音 在将放大电路10的输出设置为接地的ACG模式的情况下,如图8所示。
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公开(公告)号:US20230301617A1
公开(公告)日:2023-09-28
申请号:US18125760
申请日:2023-03-24
发明人: Makoto YOSHIDA , Kunimasa YAGI , Mikifumi SHIKIDA
摘要: A stethoscope system comprising: a plurality of sensors for collecting auscultatory sounds; and a controller which detects a first heart sound and a second heart sound of heart sounds based on a volume of the auscultatory sounds which are collected by the plurality of sensors.
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