Method for fastening a semiconductor chip on a substrate, and electronic component

    公开(公告)号:US11315898B2

    公开(公告)日:2022-04-26

    申请号:US16622161

    申请日:2018-06-06

    Abstract: A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.

    Method for Fastening a Semiconductor Chip on a Substrate, and Electronic Component

    公开(公告)号:US20200211997A1

    公开(公告)日:2020-07-02

    申请号:US16622161

    申请日:2018-06-06

    Abstract: A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.

    Light-emitting component and method of producing a light-emitting component

    公开(公告)号:US10854804B2

    公开(公告)日:2020-12-01

    申请号:US15565239

    申请日:2016-04-07

    Abstract: A light-emitting component includes a light-emitting chip and a housing including a plastic body and a reflector, the reflector includes an electrically conductive layer, the light-emitting chip includes a top side and an underside, the underside of the light-emitting chip is arranged on the plastic body, an electrical terminal on the top side of the light-emitting chip electrically conductively connects to the reflector by a bond wire, the underside of the light-emitting chip and the reflector are electrically insulated from one another, a conduction region is provided within the plastic body, thermal conductivity of the conduction region is greater than thermal conductivity of the plastic body, the conduction region adjoins the underside of the light-emitting chip, and the conduction region extends from the side of the plastic body facing the light-emitting chip as far as the side of the plastic body facing away from the light-emitting chip.

    Method for Fastening a Semiconductor Chip on a Substrate, and Electronic Component

    公开(公告)号:US20220208715A1

    公开(公告)日:2022-06-30

    申请号:US17699719

    申请日:2022-03-21

    Abstract: In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer having gold arranged between the barrier layer and the semiconductor chip, and wherein the indium-tin alloy has the following formula: InxSn1-x with 0.04≤x≤0.2.

    Method for assembling a carrier with components, pigment for assembling a carrier with a component and method for producing a pigment

    公开(公告)号:US11127890B2

    公开(公告)日:2021-09-21

    申请号:US16030714

    申请日:2018-07-09

    Inventor: Andreas Ploessl

    Abstract: The method for assembling a carrier comprises a step A), in which a plurality of pigments (100), each with an electronic component (1), is provided. Further, each pigment comprises a meltable solder material (2) directly adjoining a mounting side (10) of the component. At least 63% by volume of each pigment is formed by the solder material. The mounting side of each component has a higher wettability with the molten solder material than a top side (12) and a side surface (11) of the component. In a step B), a carrier (200) with pigment landing areas (201) is provided, the pigment landing areas having higher wettability with the molten solder material of the pigments than the regions laterally adjacent to the pigment landing areas and than the side surfaces and the top sides of the components. In a step C), the pigments are applied to the carrier. In a step D), the pigments are heated so that the solder material melts.

    COMPONENT HAVING A BUFFER LAYER AND METHOD FOR PRODUCING A COMPONENT

    公开(公告)号:US20200227604A1

    公开(公告)日:2020-07-16

    申请号:US16640062

    申请日:2018-07-19

    Abstract: A component may include a semiconductor chip, a buffer layer, a connecting layer, and a metal carrier. The semiconductor chip may include a substrate and a semiconductor body arranged thereon. The metal carrier may have a thermal expansion coefficient at least 1.5 times as great as a thermal expansion coefficient of the substrate or of the semiconductor chip. The chip may be fastened on the metal carrier by the connecting layer, and the buffer layer may have a yield stress ranging from 10 MPa. The buffer layer may have a thickness ranging from 2 um to 10 um and adjoin the chip. The substrate and the metal carrier may have a higher yield strength than the buffer layer.

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