公开(公告)号：US20230125745A1

公开(公告)日：2023-04-27

申请号：US17774870

申请日：2020-10-21

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Michael BINDER ,  Andreas RÜCKERL ,  Roland ZEISEL

IPC: H01L33/14 ,  H01L33/00 ,  H01L25/075 ,  H01L33/44 ,  H01L33/62 ,  H01L33/38

Abstract: An optoelectronic component may include a support and multiple optoelectronic semiconductor chips that can be actuated individually and independently of one another. Each semiconductor chip may include a semiconductor layer sequence. Each semiconductor chip may have an electrically insulating passivation layer on the respective lateral surface of the semiconductor layer sequence. The semiconductor chip(s) are assigned to a first group, which may be paired with a common boundary field generating device arranged on the passivation layer face facing away from the semiconductor layer sequence at an active zone for each semiconductor chip of the first group. The boundary field generating device is designed to at least temporarily generate an electric field in the boundary regions of the active zone so that a flow of current through the semiconductor layer sequences can be controlled in the boundary regions during the operation of the semiconductor chips of the first group.

公开(公告)号：US20220163564A1

公开(公告)日：2022-05-26

申请号：US17440912

申请日：2020-03-09

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Michael BERGLER ,  Roland ZEISEL

IPC: G01R1/073 ,  G01R1/04

Abstract: A method for electrically contacting components in a semiconductor wafer includes providing a flexible board comprising a first main surface on which a plurality of conductor tracks are arranged, positioning the board with respect to a semiconductor wafer such that the first main surface of the board faces the semiconductor wafer, the board is bent and pressed onto the semiconductor wafer in such a way that contact elements of a plurality of components arranged in a row in the semiconductor wafer come into contact with the conductor tracks, and electrical signals are applied to the components through the conductor tracks.

公开(公告)号：US20200168472A1

公开(公告)日：2020-05-28

申请号：US16714447

申请日：2019-12-13

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Andreas RUECKERL ,  Roland ZEISEL ,  Simeon KATZ

IPC: H01L21/3213 ,  H01L31/0304 ,  H01S5/22 ,  H01L33/44 ,  H01L33/00 ,  H01L31/0236 ,  H01L31/0232 ,  H01L21/02

Abstract: The invention relates to a method for structuring a nitride layer (2), comprising the following steps: A) providing a nitride layer (2) formed with silicon nitride of a first type, B) defining regions (40) of said nitride layer (2) to be transformed, and C) inserting the nitride layer (2) into a transformation chamber for the duration of a transformation period, said transformation period being selected such that—at least 80% of the nitride layer (2) regions (40) to be transformed are transformed into oxide regions (41) formed with silicon oxide, and—remaining nitride layer (2) regions (21) remain at least 80% untransformed.

公开(公告)号：US20210356496A1

公开(公告)日：2021-11-18

申请号：US17282622

申请日：2019-10-01

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Michael BERGLER ,  Roland ZEISEL

IPC: G01R1/073 ,  G01R31/26

Abstract: A device for processing a multiplicity of semiconductor chips in a wafer assemblage includes an electrically conductive carrier for contacting rear contacts of the semiconductor chips, an electrically conductive film for contacting front contacts of the semiconductor chips that are situated opposite the rear contacts, and a squeegee, which is displaceable relative to the film and is configured to press a region of the film in the direction toward the carrier.

公开(公告)号：US20180040485A1

公开(公告)日：2018-02-08

申请号：US15552258

申请日：2016-02-19

Applicant: OSRAM Opto Semiconductors GmbH

Inventor： Andreas RUECKERL ,  Roland ZEISEL ,  Simeon KATZ

IPC: H01L21/3213 ,  H01L33/00 ,  H01S5/22 ,  H01L31/0232 ,  H01L31/0236 ,  H01L31/0304 ,  H01L33/44 ,  H01L21/02

CPC classification number: H01L21/3213 ,  H01L21/02389 ,  H01L31/02327 ,  H01L31/02366 ,  H01L31/03044 ,  H01L33/0075 ,  H01L33/44 ,  H01L2933/0025 ,  H01S5/22

Abstract: The invention relates to a method for structuring a nitride layer (2), comprising the following steps: A) providing a nitride layer (2) formed with silicon nitride of a first type, B) defining regions (40) of said nitride layer (2) to be transformed, and C) inserting the nitride layer (2) into a transformation chamber for the duration of a transformation period, said transformation period being selected such that—at least 80% of the nitride layer (2) regions (40) to be transformed are transformed into oxide regions (41) formed with silicon oxide, and—remaining nitride layer (2) regions (21) remain at least 80% untransformed.