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公开(公告)号：US07800959B2
公开(公告)日：2010-09-21
申请号：US12233922
申请日：2008-09-19
IPC分类号： G11C16/00
CPC分类号： G11C7/1048 , G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/41 , G11C11/419 , G11C29/12 , G11C29/12005 , G11C2029/1204
摘要： A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
摘要翻译： 存储器具有存储器单元阵列，列逻辑，写驱动器，电压检测器和自举电路。 存储器单元的阵列耦合到位线对和字线对。 列逻辑耦合到阵列，并用于将选定的一对位线耦合到一对数据线。 写驱动器耦合到该对数据线。 当写入驱动器在一对数据线的写入期间，当一对数据线的第一数据线的电压下降到低于第一电平时，电压检测器提供启动升压信号。 自举电路响应于升压使能信号而降低第一数据线的电压。 当编译器中的位线上的存储单元数量可能显着变化时，这是特别有益的。
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公开(公告)号：US20100074032A1
公开(公告)日：2010-03-25
申请号：US12233922
申请日：2008-09-19
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C5/145 , G11C7/1078 , G11C7/1096 , G11C11/41 , G11C11/419 , G11C29/12 , G11C29/12005 , G11C2029/1204
摘要： A memory has an array of memory cells, column logic, a write driver, a voltage detector, and a bootstrap circuit. The array of memory cells is coupled to pairs of bit lines and word lines. The column logic is coupled to the array and is for coupling a selected pair of bit lines to a pair of data lines. The write driver is coupled to the pair of data lines. The voltage detector provides an initiate boost signal when a voltage of a first data line of the pair of data lines drops below a first level during the writing of the pair of data lines by the write driver. The bootstrap circuit reduces the voltage of the first data line in response to the boost enable signal. This is particularly beneficial when the number of memory cells on a bit line can vary significantly as in a compiler.
摘要翻译： 存储器具有存储器单元阵列，列逻辑，写驱动器，电压检测器和自举电路。 存储器单元的阵列耦合到位线对和字线对。 列逻辑耦合到阵列，并用于将选定的一对位线耦合到一对数据线。 写驱动器耦合到该对数据线。 当写入驱动器在一对数据线的写入期间，当一对数据线的第一数据线的电压下降到低于第一电平时，电压检测器提供启动升压信号。 自举电路响应于升压使能信号而降低第一数据线的电压。 当编译器中的位线上的存储单元数量可能显着变化时，这是特别有益的。
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公开(公告)号：US07292485B1
公开(公告)日：2007-11-06
申请号：US11461200
申请日：2006-07-31
IPC分类号： G11C5/14
CPC分类号： G11C5/14 , G11C11/413
摘要： A memory circuit has a memory array with a first line of memory cells, a second line of memory cells, a first power supply terminal, a first capacitance structure, a first power supply line coupled to the first line of memory cells; and a second power supply line coupled to the second line of memory cells. For the case where the second line of memory cells is selected for writing, a switching circuit couples the power supply terminal to the first power supply line, decouples the first power supply line from the second line of memory cells, and couples the second power supply line to the first capacitance structure. The result is a reduction in power supply voltage to the selected line of memory cells by charge sharing with the capacitance structure. This provides more margin in the write operation on a cell in the selected line of memory cells.
摘要翻译： 存储器电路具有存储器阵列，其具有第一行存储器单元，第二行存储器单元，第一电源端子，第一电容结构，耦合到第一行存储器单元的第一电源线; 以及耦合到第二行存储器单元的第二电源线。 对于第二行存储单元被选择用于写入的情况，开关电路将电源端子耦合到第一电源线，使第一电源线与第二行存储单元分离，并将第二电源 线到第一个电容结构。 结果是通过与电容结构的电荷共享来降低对选定的存储单元线的电源电压。 这在存储器单元的所选行中的单元上的写入操作中提供了更多的余量。
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公开(公告)号：US09318163B2
公开(公告)日：2016-04-19
申请号：US13789017
申请日：2013-03-07
摘要： In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it.
摘要翻译： 根据至少一个实施例，系统（例如，片上系统（SOC）或其他系统）上的时钟计数器被用于对预定义的内存中的存储器时钟的时钟边缘的数量进行计数 基于预定的系统时钟频率，因此确定存储器阵列（例如，非易失性存储器（NVM）阵列或其他存储器阵列）的存储器时钟是否正确。 系统被引导等待直到计数在预期的范围内，然后再转到启动过程中的下一个步骤。 如果超过允许的最大启动时间，系统会发送错误信号，以便应用程序可以对其进行响应。
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公开(公告)号：US5441914A
公开(公告)日：1995-08-15
申请号：US236076
申请日：1994-05-02
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L23/532 , H01L21/283 , H01L21/314
CPC分类号： H01L23/53271 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L21/32139 , H01L2924/0002 , Y10S148/012
摘要： In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
摘要翻译： 在一个实施例中，通过在图案化硅化钨层（32）和图案化硅化钨层（32）之间形成薄硅层（30）来防止图案化的氮化硅抗反射层（26）从下面的图案化硅化钨层（32） 覆盖图案化的氮化硅抗反射层（26）。
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公开(公告)号：US5872385A
公开(公告)日：1999-02-16
申请号：US666722
申请日：1996-06-18
IPC分类号： H01L21/027 , H01L21/28 , H01L21/3213 , H01L23/532 , H01L31/0232
CPC分类号： H01L23/53271 , H01L21/0276 , H01L21/28061 , H01L21/28123 , H01L21/32137 , H01L21/32139 , H01L2924/0002 , Y10S148/012
摘要： In one embodiment, delamination of a patterned silicon nitride anti-reflective layer (26) from an underlying patterned tungsten silicide layer (32), is prevented by forming a thin silicon layer (30) between the patterned tungsten silicide layer (32) and the overlying patterned silicon nitride anti-reflective layer (26).
摘要翻译： 在一个实施例中，通过在图案化硅化钨层（32）和图案化硅化钨层（32）之间形成薄硅层（30）来防止图案化的氮化硅抗反射层（26）从下面的图案化硅化钨层（32） 覆盖图案化的氮化硅抗反射层（26）。
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公开(公告)号：US20140254299A1
公开(公告)日：2014-09-11
申请号：US13789017
申请日：2013-03-07
摘要： In accordance with at least one embodiment, a clock counter on a system (for example, a system-on-a-chip (SOC) or other system) is utilized to count a number of a clock edges of a memory clock within a predefined time based on a predetermined system clock frequency and, therefore, to determine whether the memory clock for a memory array (for example, a non-volatile memory (NVM) array or other memory array) is correct or not. The system is directed to wait until the count is within an expected range before moving to the next step in a start-up procedure. If the maximum allowed start-up time is exceeded, an error signal is sent to the system such that the application can react to it.
摘要翻译： 根据至少一个实施例，系统（例如，片上系统（SOC）或其他系统）上的时钟计数器被用于对预定义的内存中的存储器时钟的时钟边缘的数量进行计数 基于预定的系统时钟频率，因此确定存储器阵列（例如，非易失性存储器（NVM）阵列或其他存储器阵列）的存储器时钟是否正确。 系统被引导等待直到计数在预期的范围内，然后再转到启动过程中的下一个步骤。 如果超过允许的最大启动时间，系统会发送错误信号，以便应用程序可以对其进行响应。
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