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    Process for forming a semiconductor device and a static-random-access memory cell
    3.
    发明授权
    Process for forming a semiconductor device and a static-random-access memory cell 失效
    用于形成半导体器件和静态随机存取存储器单元的工艺

    公开(公告)号：US5721167A

    公开(公告)日：1998-02-24

    申请号：US797142

    申请日：1997-02-10

    申请人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

    发明人： Chitra Subramanian ,  James D. Hayden ,  Olubunmi Adetutu ,  Dean Denning ,  Arkalgud R. Sitaram

    IPC分类号： H01L21/8244

    CPC分类号： H01L27/11

    摘要： A semiconductor device (10) is formed having an SRAM array with a plurality of SRAM cells. In forming the access and latch transistors, two different gate electrode compositions are used to form the access and latch transistors. More specifically, a dielectric layer (22) is formed between two conductive layers (26 and 28) within the gate electrode (52) for the access transistors while the dielectric layer is not formed between the two conductive layers (26 and 28) for the latch transistors. This structure allows an increase in the beta ratio for the SRAM cell thereby making a more stable SRAM cell without having to use diffused resistors between the access transistors in storage nodes or by having to form a differential thickness between the gate dielectric layers for the latch transistors and the access transistors.

    摘要翻译： 形成具有具有多个SRAM单元的SRAM阵列的半导体器件（10）。 在形成访问和锁存晶体管时，使用两种不同的栅电极组合物来形成访问和锁存晶体管。 更具体地，在用于存取晶体管的栅电极（52）内的两个导电层（26和28）之间形成介电层（22），而在两个导电层（26和28）之间不形成介电层，用于 锁存晶体管。 该结构允许增加SRAM单元的β比，从而形成更稳定的SRAM单元，而不必在存储节点中的存取晶体管之间使用扩散电阻，或者必须在用于锁存晶体管的栅介质层之间形成差分厚度 和存取晶体管。

    Method for forming a transistor having silicided regions
    5.
    发明授权
    Method for forming a transistor having silicided regions 失效
    用于形成具有硅化物区域的晶体管的方法

    公开(公告)号：US5352631A

    公开(公告)日：1994-10-04

    申请号：US991801

    申请日：1992-12-16

    申请人： Arkalgud R. Sitaram ,  James R. Pfiester

    发明人： Arkalgud R. Sitaram ,  James R. Pfiester

    IPC分类号： H01L21/225 ,  H01L21/285 ,  H01L21/336 ,  H01L21/283

    CPC分类号： H01L29/66507 ,  H01L21/28518 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66628 ,  H01L21/2257 ,  H01L29/66545

    摘要： A process for forming a transistor (10) begins by providing a substrate (12). Field oxide regions (14) or equivalent isolation is formed overlying or within the substrate (12). A gate oxide (16) and a conductive layer (18) are formed. A masking layer (20) is formed overlying the conductive layer (18). The masking layer (20) and the conductive layer (18) are etched to form a gate electrode and define a drain region (19) and a source region (21). Spacers (22) are formed adjacent the gate electrode. First silicided regions (26) are formed over the source and drain regions (21 and 19 respectively). The masking layer prevents the gate electrode from siliciding. The masking layer (20) is removed and a second silicided region (30) is formed overlying the gate electrode. The second silicided region (30) and the silicided regions (26) are made of different silicides.

    摘要翻译： 用于形成晶体管（10）的工艺通过提供衬底（12）开始。 场氧化物区域（14）或等效隔离形成在衬底（12）之上或之内。 形成栅极氧化物（16）和导电层（18）。 形成覆盖导电层（18）的掩模层（20）。 蚀刻掩模层（20）和导电层（18）以形成栅电极并限定漏区（19）和源极区（21）。 隔板（22）形成在栅电极附近。 在源极和漏极区（分别为21和19）上形成第一硅化区（26）。 掩模层防止栅电极硅化。 去除掩模层（20），并且形成覆盖栅电极的第二硅化区域（30）。 第二硅化物区域（30）和硅化物区域（26）由不同的硅化物制成。

    Contact structure and process for formation
    6.
    发明授权
    Contact structure and process for formation 失效
    接触结构和形成过程

    公开(公告)号：US06291888B1

    公开(公告)日：2001-09-18

    申请号：US09461251

    申请日：1999-12-15

    申请人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

    发明人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

    IPC分类号： H01L214763

    CPC分类号： H01L21/76805 ,  H01L21/76831 ,  H01L21/76895

    摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive nodules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

    摘要翻译： 实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。 在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。 当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电结核（52）位于凹陷（42）内。 在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

    Method of making a contact structure
    7.
    发明授权
    Method of making a contact structure 失效
    制作接触结构的方法

    公开(公告)号：US06037246A

    公开(公告)日：2000-03-14

    申请号：US715303

    申请日：1996-09-17

    申请人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

    发明人： Mousumi Bhat ,  Mark D. Hall ,  Arkalgud R. Sitaram ,  Michael P. Woo

    IPC分类号： H01L21/768 ,  H01L21/4763

    CPC分类号： H01L21/76805 ,  H01L21/76831 ,  H01L21/76895

    摘要： Electrical shorts and leakage paths are virtually eliminated by recessing conductive nodules (52) away from a conductor (72) or not forming the conductive nodules at all. In one embodiment, the refractory metal containing material (52) is recessed from the edge of the opening (32). When forming a nitride layer (54) within the opening (32), conductive nodules (52) are formed from a portion of the refractory metal containing material (20) such that the conductive modules (52) lie within the recession (42). In another embodiment, an oxide layer (82, 102) is formed adjacent to the refractory metal containing material (20) before forming a nitride layer (84, 112).

    摘要翻译： 实际上通过使导电结节（52）远离导体（72）凹陷或完全不形成导电结节来消除电短路和漏电路径。 在一个实施例中，含难熔金属材料（52）从开口（32）的边缘凹进。 当在开口（32）内形成氮化物层（54）时，导电结核（52）由含难熔金属材料（20）的一部分形成，使得导电模块（52）位于凹陷（42）内。 在另一个实施例中，在形成氮化物层（84,112）之前，邻近难熔金属材料（20）形成氧化物层（82,102）。

    Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction
    8.
    发明授权
    Method for forming self-aligned silicide in a semiconductor device using vapor phase reaction 失效
    在使用气相反应的半导体器件中形成自对准硅化物的方法

    公开(公告)号：US5605865A

    公开(公告)日：1997-02-25

    申请号：US416124

    申请日：1995-04-03

    申请人： Papu D. Maniar ,  Arkalgud R. Sitaram

    发明人： Papu D. Maniar ,  Arkalgud R. Sitaram

    IPC分类号： H01L21/285

    CPC分类号： H01L21/28518

    摘要： Self-aligned silicide regions (24) are formed in a semiconductor device (10) using vapor phase reaction. A chemical vapor deposition system (40) is used, but rather than depositing a blanket silicide material, a precursor (48) is introduced into the reaction chamber (42) and reacts with only exposed silicon and polysilicon members of the device. The reaction is assisted by heating the substrate to a temperature at which the precursor is volatile. Because the precursor source reacts only with exposed silicon and polysilicon regions, subsequent etch steps are unnecessary. In one form, cobalt silicide regions are formed using a cobalt carbonyl as the precursor source.

    摘要翻译： 使用气相反应在半导体器件（10）中形成自对准硅化物区域（24）。 使用化学气相沉积系统（40），而不是沉积覆盖层硅化物材料，前体（48）被引入反应室（42）中，并且仅与设备的暴露的硅和多晶硅构件反应。 通过将基底加热到前体挥发性的温度来辅助反应。 因为前体源仅与暴露的硅和多晶硅区域反应，所以后续的蚀刻步骤是不必要的。 在一种形式中，使用羰基钴作为前体源形成钴硅化物区域。