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1.再颁专利Memory system performing fast access to a memory location by omitting the transfer of a redundant address 有权存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问公开(公告)号：USRE41589E1
公开(公告)日：2010-08-24
申请号：US10290367
申请日：2002-11-08
IPC分类号： G06F12/06
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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2.发明授权Memory system performing fast access to a memory location by omitting the transfer of a redundant address 有权存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问
公开(公告)号：US6154807A
公开(公告)日：2000-11-28
申请号：US188902
申请日：1998-11-10
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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公开(公告)号：US06292867B1
公开(公告)日：2001-09-18
申请号：US09641913
申请日：2000-08-21
IPC分类号： G06F1202
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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4.发明授权Memory system performing fast access to a memory location by omitting transfer of a redundant address 失效存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问
公开(公告)号：US5873122A
公开(公告)日：1999-02-16
申请号：US815600
申请日：1997-03-12
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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5.发明授权Method for prefetching pointer-type data structure and information processing apparatus therefor 失效用于预取指针型数据结构的方法及其信息处理装置
公开(公告)号：US5652858A
公开(公告)日：1997-07-29
申请号：US455335
申请日：1995-05-31
申请人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
发明人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
CPC分类号： G06F9/30043 , G06F12/0862 , G06F9/383 , G06F2212/1024 , G06F2212/6022 , G06F2212/6028
摘要： In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.
摘要翻译： 为了允许指针型数据结构的预取，加载指令的指令字具有指示符提示，指示由指令加载的数据包括指定下一个数据的地址的指针。 当CPU执行这样的指令，并且从主存储器加载由该指令请求的数据时，存储器接口电路中的预取电路使用该指针从主存储器读取包含由该指针指定的数据的块，然后 临时存储在其中提供的预取缓冲器中。 当CPU执行请求读取由该指针指定的数据的加载指令时，该存储块中的数据通过处理器接口电路和高速缓存控制电路提供给CPU。
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6.发明授权Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus 失效集成电路数据处理器，包括用于在不停用地址总线的情况下去激活数据总线的驱动的控制引脚
公开(公告)号：US5557760A
公开(公告)日：1996-09-17
申请号：US117681
申请日：1993-09-08
申请人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
发明人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
CPC分类号： G06F12/0893 , G06F13/4072
摘要： A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.
摘要翻译： 用于具有高速缓存RAM和主存储器的数据处理系统中的处理器具有控制引脚，用于在写周期期间停用数据总线的驱动而不停用地址总线的驱动。 在无需附加地址存储电路的执行写入操作之后的高速缓存存储操作期间，该能力是有用的。 特别地，在高速缓存存储操作期间，处理器可以驱动地址总线，同时处理器的数据总线的控制是浮动的。 然后，主存储器中的数据可以放在数据总线上并传输到高速缓存中。 一旦将数据传输到高速缓冲存储器，可以完成原始写入操作。
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公开(公告)号：US08780364B2
公开(公告)日：2014-07-15
申请号：US13362274
申请日：2012-01-31
申请人： Tasuku Kohara , Hiroshi Takeda , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Masaaki Kawamura
发明人： Tasuku Kohara , Hiroshi Takeda , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Masaaki Kawamura
IPC分类号： G06F15/00
CPC分类号： H04N1/00408 , G03G15/5016 , G03G15/502 , G03G21/1657 , G06F3/1204 , G06F3/121 , G06F3/1234 , G06F3/1279 , G06F3/1292 , H04N1/00538 , H04N1/0083 , H04N2201/0091
摘要： An electronic apparatus includes a main body of the electronic apparatus; an operation unit including an operation block having a display unit, the operation block being detachable with respect to the main body of the electronic apparatus, and the operation block enabling at least a bidirectional wireless communication with the main body of the electronic apparatus; and a detection unit configured to detect relative positional information between the operation block and the main body of the electronic apparatus, when the operation block is detached from the main body of the electronic apparatus. The operation block being detached from the main body of the electronic apparatus is able to display information corresponding to the relative positional information on the display unit, in accordance with a condition of the main body of the electronic apparatus.
摘要翻译： 电子设备包括电子设备的主体; 操作单元，包括具有显示单元的操作块，所述操作块相对于所述电子设备的主体可拆卸，所述操作块至少能够与所述电子设备的主体进行双向无线通信; 以及检测单元，被配置为当所述操作块与所述电子设备的主体分离时，检测所述操作块与所述电子设备的主体之间的相对位置信息。 与电子设备的主体分离的操作块能够根据电子设备的主体的状态显示与显示单元上的相对位置信息相对应的信息。
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公开(公告)号：US08462393B2
公开(公告)日：2013-06-11
申请号：US13041825
申请日：2011-03-07
申请人： Tasuku Kohara , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Hiroshi Takeda , Hiroki Tsuruoka
发明人： Tasuku Kohara , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Hiroshi Takeda , Hiroki Tsuruoka
IPC分类号： H04N1/04
CPC分类号： H04N1/2112 , G03G15/36 , G03G15/502 , G03G15/605 , G03G2215/00177 , H04N1/00278 , H04N1/00347 , H04N1/00562 , H04N2101/00 , H04N2201/0082 , H04N2201/0084 , H04N2201/0089
摘要： An image reading apparatus includes a scanner part reading an original on a contact glass, and a projector part projecting image information onto the contact glass as first image displaying. The projector part projects thumbnails or an image to have an image processing operation carried out or be printed. The display part carries out second image displaying obtained from reducing the first image displaying in size. At a time of the scanner part being operated, transmittance of the contact glass is increased and the projector part stops projecting the image information, and at a time of the scanner part not being operated, the transmittance of the contact glass is decreased and the projector part carries out the first image displaying. Setting of the image processing operation for the image data is reflected on the first image displaying and the second image displaying.
摘要翻译： 图像读取装置包括：将接触玻璃上的原件读取的扫描仪部分，以及将图像信息投影到接触玻璃上作为第一图像显示的投影仪部。 投影仪部分投影缩略图或图像以执行或打印图像处理操作。 显示部分执行从减小尺寸的第一图像获得的第二图像显示。 在操作扫描仪部分时，接触玻璃的透射率增加，并且投影仪部分停止投影图像信息，并且在扫描仪部分未被操作时，接触玻璃的透射率降低，并且投影仪 部分执行第一图像显示。 图像数据的图像处理操作的设置反映在第一图像显示和第二图像显示上。
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9.发明申请SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME 审中-公开半导体器件，半导体器件及其制造方法公开(公告)号：US20120313172A1
公开(公告)日：2012-12-13
申请号：US13489128
申请日：2012-06-05
IPC分类号： H01L27/088 , H01L21/762 , H01L21/20 , H01L29/02
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/76283 , H01L21/84 , H01L27/1207 , H01L29/78648
摘要： This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.
摘要翻译： 本发明提供一种具有减小的晶体管特性变化的半导体器件。 半导体器件具有SOI衬底，第一元件隔离绝缘层，第一和第二导电型晶体管以及第一和第二后栅极触点。 SOI衬底具有具有第一和第二导电类型层，绝缘层和半导体层的半导体衬底。 第一元件隔离绝缘层被埋在SOI衬底中，具有到达第一导电类型层的下端，并且将第一元件区域与第二元件区域隔离。 第一和第二导电类型晶体管分别位于第一和第二元件区域中，并且在半导体层中形成有各自的沟道区。 第一和第二背栅极触点分别耦合到第一和第二元件区域中的第二导电类型层。
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公开(公告)号：US20120200874A1
公开(公告)日：2012-08-09
申请号：US13362274
申请日：2012-01-31
申请人： Tasuku KOHARA , Hiroshi Takeda , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Masaaki Kawamura
发明人： Tasuku KOHARA , Hiroshi Takeda , Kazuo Koike , Kenichi Yamada , Taisuke Omi , Tsuyoshi Endoh , Masaaki Kawamura
CPC分类号： H04N1/00408 , G03G15/5016 , G03G15/502 , G03G21/1657 , G06F3/1204 , G06F3/121 , G06F3/1234 , G06F3/1279 , G06F3/1292 , H04N1/00538 , H04N1/0083 , H04N2201/0091
摘要： An electronic apparatus includes a main body of the electronic apparatus; an operation unit including an operation block having a display unit, the operation block being detachable with respect to the main body of the electronic apparatus, and the operation block enabling at least a bidirectional wireless communication with the main body of the electronic apparatus; and a detection unit configured to detect relative positional information between the operation block and the main body of the electronic apparatus, when the operation block is detached from the main body of the electronic apparatus. The operation block being detached from the main body of the electronic apparatus is able to display information corresponding to the relative positional information on the display unit, in accordance with a condition of the main body of the electronic apparatus.
摘要翻译： 电子设备包括电子设备的主体; 操作单元，包括具有显示单元的操作块，所述操作块相对于所述电子设备的主体可拆卸，所述操作块至少能够与所述电子设备的主体进行双向无线通信; 以及检测单元，被配置为当所述操作块与所述电子设备的主体分离时，检测所述操作块与所述电子设备的主体之间的相对位置信息。 与电子设备的主体分离的操作块能够根据电子设备的主体的状态显示与显示单元上的相对位置信息相对应的信息。
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