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1.再颁专利Memory system performing fast access to a memory location by omitting the transfer of a redundant address 有权存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问公开(公告)号：USRE41589E1
公开(公告)日：2010-08-24
申请号：US10290367
申请日：2002-11-08
IPC分类号： G06F12/06
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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2.发明授权Memory system performing fast access to a memory location by omitting the transfer of a redundant address 有权存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问
公开(公告)号：US6154807A
公开(公告)日：2000-11-28
申请号：US188902
申请日：1998-11-10
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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公开(公告)号：US06292867B1
公开(公告)日：2001-09-18
申请号：US09641913
申请日：2000-08-21
IPC分类号： G06F1202
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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4.发明授权Memory system performing fast access to a memory location by omitting transfer of a redundant address 失效存储器系统通过省略冗余地址的传输来执行对存储器位置的快速访问
公开(公告)号：US5873122A
公开(公告)日：1999-02-16
申请号：US815600
申请日：1997-03-12
CPC分类号： G06F12/0215 , G06F13/1631
摘要： A data processing system including a processor LSI and a DRAM divided into banks, for increasing a ratio of using a fast operation mode for omitting transfer of a row address to the DRAM and for minimizing the amount of logics external to the processor LSI. The processor LSI includes row address registers for holding recent row addresses corresponding to the banks. The contents of the row address registers are compared with an accessed address by a comparator to check for each bank whether the fast operation mode is possible. As long as the row address does not change in each bank, the fast operation mode can be used, thus making it possible to speed up operations, for example in block copy processing.
摘要翻译： 一种数据处理系统，包括处理器LSI和划分为存储体的DRAM，用于增加使用快速操作模式以省略将行地址传送到DRAM的比例，以及最小化处理器LSI外部的逻辑量。 处理器LSI包括行地址寄存器，用于保存对应于存储体的最近行地址。 通过比较器将行地址寄存器的内容与访问地址进行比较，以检查每个存储区是否可以进行快速操作模式。 只要每个行中的行地址不变化，可以使用快速操作模式，从而可以加快操作，例如在块复制处理中。
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5.发明授权Method for prefetching pointer-type data structure and information processing apparatus therefor 失效用于预取指针型数据结构的方法及其信息处理装置
公开(公告)号：US5652858A
公开(公告)日：1997-07-29
申请号：US455335
申请日：1995-05-31
申请人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
发明人： Tetsuhiko Okada , Osamu Nishii , Hiroshi Takeda
CPC分类号： G06F9/30043 , G06F12/0862 , G06F9/383 , G06F2212/1024 , G06F2212/6022 , G06F2212/6028
摘要： In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.
摘要翻译： 为了允许指针型数据结构的预取，加载指令的指令字具有指示符提示，指示由指令加载的数据包括指定下一个数据的地址的指针。 当CPU执行这样的指令，并且从主存储器加载由该指令请求的数据时，存储器接口电路中的预取电路使用该指针从主存储器读取包含由该指针指定的数据的块，然后 临时存储在其中提供的预取缓冲器中。 当CPU执行请求读取由该指针指定的数据的加载指令时，该存储块中的数据通过处理器接口电路和高速缓存控制电路提供给CPU。
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6.发明授权Integrated circuit data processor including a control pin for deactivating the driving of a data bus without deactivating that of an address bus 失效集成电路数据处理器，包括用于在不停用地址总线的情况下去激活数据总线的驱动的控制引脚
公开(公告)号：US5557760A
公开(公告)日：1996-09-17
申请号：US117681
申请日：1993-09-08
申请人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
发明人： Osamu Nishii , Takashi Inagawa , Makoto Hanawa , Hiroshi Takeda
CPC分类号： G06F12/0893 , G06F13/4072
摘要： A processor for use in a data processing system with a cache RAM and main memory has a control pin for deactivating the driving of the data bus without deactivating that of the address bus during a write cycle. This capability is useful during a cache storing operation following a miss for performing a write operation without the requirement of additional address storing circuitry. In particular, during a cache storing operation, the processor can drive the address bus while control of the data bus by the processor is floated. Then, the data in main memory can be put on the data bus and transferred into the cache memory. Once the data is transferred to the cache memory, the original write operation can be completed.
摘要翻译： 用于具有高速缓存RAM和主存储器的数据处理系统中的处理器具有控制引脚，用于在写周期期间停用数据总线的驱动而不停用地址总线的驱动。 在无需附加地址存储电路的执行写入操作之后的高速缓存存储操作期间，该能力是有用的。 特别地，在高速缓存存储操作期间，处理器可以驱动地址总线，同时处理器的数据总线的控制是浮动的。 然后，主存储器中的数据可以放在数据总线上并传输到高速缓存中。 一旦将数据传输到高速缓冲存储器，可以完成原始写入操作。
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7.发明授权Data processing system with branch target addressing using upper and lower bit permutation 失效具有分支目标寻址的数据处理系统使用高位和低位置换公开(公告)号：US08145889B2
公开(公告)日：2012-03-27
申请号：US12912836
申请日：2010-10-27
申请人： Osamu Nishii
发明人： Osamu Nishii
IPC分类号： G06F9/00
CPC分类号： G06F9/322 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3806
摘要： A data processor or a data processing system used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. A multiple with which the displacement is multiplied can be changed in accordance with the mode.
摘要翻译： 在兼容模式下使用的数据处理器或数据处理系统，其中指定逻辑地址空间的地址的位数在通过分支指令的位移的扩展引用分支地址表时变化。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 可以根据该模式来改变与该位移相乘的倍数。
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8.发明授权Data processing system to calculate indexes into a branch target address table based on a current operating mode 失效数据处理系统根据当前的运行模式计算索引到分支目标地址表中公开(公告)号：US07836286B2
公开(公告)日：2010-11-16
申请号：US12013468
申请日：2008-01-13
申请人： Osamu Nishii
发明人： Osamu Nishii
IPC分类号： G06F9/44
CPC分类号： G06F9/322 , G06F9/3016 , G06F9/30181 , G06F9/30189 , G06F9/3806
摘要： The present invention provides a data processor or a data processing system which can be used in compatible modes among which the number of bits of an address specifying a logical address space varies at the time of referring to a branch address table by extension of displacement of a branch instruction. At the time of generating a branch address of a first branch instruction, the data processor or the data processing system optimizes a multiple with which a displacement is multiplied in accordance with the number of bits of an address specifying a logical address space, adds extended address information to the value of a register, and refers to a branch address table with address information obtained by the addition. The referred information is used as a branch address. To be adapted to a compatible mode using different number of bits of an address specifying a logical address space, it is sufficient to change a multiple with which the displacement is multiplied in accordance with the mode.
摘要翻译： 本发明提供一种数据处理器或数据处理系统，其可以在兼容模式中使用，其中指定逻辑地址空间的地址的位数在通过扩展a的扩展引用分支地址表时变化 分支指令。 在生成第一分支指令的分支地址时，数据处理器或数据处理系统根据指定逻辑地址空间的地址的位数来优化与该位移相乘的倍数，将扩展地址 信息到寄存器的值，并且是指通过添加获得的具有地址信息的分支地址表。 所引用的信息用作分支地址。 为了适应于使用指定逻辑地址空间的地址的不同位数的兼容模式，根据该模式来改变与该位移相乘的倍数就足够了。
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公开(公告)号：US20100005324A1
公开(公告)日：2010-01-07
申请号：US12346268
申请日：2008-12-30
申请人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
发明人： Yonetaro TOTSUKA , Koichiro Ishibashi , Hiroyuki Mizuno , Osamu Nishii , Kunio Uchiyama , Takanori Shimura , Asako Sekine , Yoichi Katsuki , Susumu Narita
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172 , Y02D50/20
摘要： The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
摘要翻译： 本发明的特征在于：处理器主电路，用于在处理器芯片上执行程序指令串; 衬底偏置切换单元，用于切换施加到处理器主电路的衬底的衬底偏压的电压; 以及操作模式控制单元，用于响应于执行处理器主电路中的待机模式的指令，控制所述衬底偏置切换单元，使得所述偏置切换到所述处理器主电路的电压 待机模式，并且为了响应于来自外部的待机释放的中断来控制衬底偏置切换单元，使得偏置被切换到用于正常模式的电压，并且还用于释放 在切换到其上的偏置电压已经稳定之后，处理器主电路的待机重新开始操作。
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公开(公告)号：US07143230B2
公开(公告)日：2006-11-28
申请号：US10752569
申请日：2004-01-08
申请人： Kunio Uchiyama , Osamu Nishii
发明人： Kunio Uchiyama , Osamu Nishii
IPC分类号： G06F12/00
CPC分类号： G11C8/18 , G11C7/1006 , G11C7/1072 , G11C8/12 , H04N19/423 , H04N19/61
摘要： A main storage apparatus is a synchronous dynamic memory having a plurality of memory banks and a mode register for determining an operation mode, a main storage controller is coupled to a processor and the main storage apparatus, and means to realize controlling of parallel access to a plurality of banks of the memory and controlling of setting of an operation mode to the built-in register is arranged in the main storage controller. Accordingly, the use of a conventional processor of high generality and a conventional memory can be ensured.
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