Digital signal decoding apparatus
    1.
    发明授权
    Digital signal decoding apparatus 失效
    数字信号解码装置

    公开(公告)号:US5461378A

    公开(公告)日:1995-10-24

    申请号:US118456

    申请日:1993-09-08

    IPC分类号: H03M7/30 H04B1/66

    CPC分类号: H04B1/665

    摘要: There is provided a decoding apparatus adapted for decoding a coded signal from a coding apparatus adapted to divide an input, digital signal into signals in frequency bands by using at least one filter to divide respective filter outputs into blocks every plural words to carry out a first block floating processing every respective blocks to further implement an orthogonal transform processing to the signal which has been subjected to the first block floating processing to thereby conduct frequency analysis thereafter to divide the orthogonally transformed output into blocks every plural words to carry out a second block floating processing every respective blocks, wherein after the second block floating is released by using a predetermined number of inverse floating circuits, the coded signal is restored to a signal on the time base by inverse orthogonal transform processing at a predetermined number of IMDCT circuits, and the first block floating is released in the process of the inverse orthogonal transform operation.

    摘要翻译: 提供了一种解码装置,用于对来自编码装置的编码信号进行解码,该编码装置适于通过使用至少一个滤波器将输入的数字信号划分成频带的信号,以将每个滤波器的输出分成多个字来进行第一 对每个块进行块浮动处理,以进一步对已经经过第一块浮动处理的信号执行正交变换处理,从而进行频率分析,然后将正交变换的输出划分为每个多个字块,以执行第二块浮置 处理每个各个块,其中在通过使用预定数量的反向浮动电路来释放第二块浮动之后,通过在预定数量的IMDCT电路上的逆正交变换处理将编码信号恢复为基于时基的信号,并且 第一块浮动在inv的过程中释放 正交变换运算。

    Digital signal coding/decoding apparatus, digital signal coding
apparatus, and digital signal decoding apparatus
    2.
    发明授权
    Digital signal coding/decoding apparatus, digital signal coding apparatus, and digital signal decoding apparatus 失效
    数字信号编码/解码装置,数字信号编码装置和数字信号解码装置

    公开(公告)号:US5381143A

    公开(公告)日:1995-01-10

    申请号:US118495

    申请日:1993-09-08

    CPC分类号: H04B14/046

    摘要: A digital signal processing system comprising a compressor, an expander and a scale-down circuit. The compressor includes non-block frequency analyzer that frequency analyzes the digital input digital signal, without dividing it into block, to provide a frequency range signal in each of plural frequency ranges. A block frequency analyzer divides the frequency range signals into blocks and performs a block frequency analysis of each block of the frequency range signals to provide a block of spectral coefficients. A quantizer quantizes the block of spectral coefficients from the block frequency analyzer to provide a block of a compressed signal. The expander includes a block frequency synthesizer that performs a block frequency synthesis to transform, from the frequency domain to the time domain, the spectral coefficients in each of the frequency ranges in each block of the compressed signal to provide, in each of the frequency ranges, a block of a reproduced frequency range signal. A non-block frequency synthesizer synthesizes the reproduced frequency range signals, without dividing them into blocks, to provide the digital output signal. Finally, the system includes a scale-down circuit that scales down values in the block frequency analysis performed by the block frequency analyzer or the block frequency synthesis performed by the block frequency synthesizer. The scale-down circuit operates to cause the noise levels resulting from scaling down the values to be different in each of the frequency ranges.

    摘要翻译: 一种数字信号处理系统,包括压缩器,扩展器和缩小电路。 压缩机包括非块频率分析仪,其频率分析数字输入数字信号,而不将其分成块,以在多个频率范围中的每一个中提供频率范围信号。 块频率分析仪将频率范围信号划分为块,并对频率范围信号的每个块执行块频率分析,以提供频谱系数块。 量化器对来自块频率分析器的频谱系数块进行量化以提供压缩信号的块。 扩展器包括块频率合成器,其执行块频率合成以从频域到时域将压缩信号的每个块中的每个频率范围中的频谱系数变换以在每个频率范围 ,再现频率范围信号的块。 非块频率合成器将再现的频率范围信号合成,而不将它们分成块,以提供数字输出信号。 最后,该系统包括一个缩小电路,其缩小由块频率分析器执行的块频率分析中的值或由块频率合成器执行的块频率合成。 降压电路用于使得在每个频率范围内将值缩小而导致的噪声水平不同。