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    Complex stress-engineered frangible structures
    2.
    发明授权
    Complex stress-engineered frangible structures 有权

    公开(公告)号：US10648491B2

    公开(公告)日：2020-05-12

    申请号：US16273397

    申请日：2019-02-12

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting

    IPC: C03C21/00 ,  F16B1/00 ,  B32B17/00 ,  C03C27/06 ,  C03C27/10 ,  C03B27/00 ,  C03B23/203 ,  C03B23/20 ,  C03C15/00 ,  C03C27/04 ,  B32B17/10

    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members. One-way crack propagation is achieved by providing a weaker member region only on the downstream side of each inter-structure bond.

    BARE DIE INTEGRATION WITH PRINTED COMPONENTS ON FLEXIBLE SUBSTRATE WITHOUT LASER CUT
    4.
    发明申请
    BARE DIE INTEGRATION WITH PRINTED COMPONENTS ON FLEXIBLE SUBSTRATE WITHOUT LASER CUT 审中-公开

    公开(公告)号：US20190124757A1

    公开(公告)日：2019-04-25

    申请号：US16190324

    申请日：2018-11-14

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Tse Nga Ng ,  Ping Mei ,  Brent S. Krusor ,  Gregory L. Whiting ,  Steven E. Ready ,  Janos Veres

    IPC: H05K1/02 ,  H01L23/00 ,  H01L21/56 ,  H05K3/14 ,  H05K1/03 ,  H05K1/18

    Abstract: Provided is a manufacturing process for electronic circuit components such as bare dies, and packaged integrated chips, among other configurations, to form electronic assemblies. The surface of the electronic circuit component carries electronic elements such as conductive traces and/or other configurations including contact pads. A method for forming an electronic assembly includes providing a tacky layer. Then an electronic circuit component is provided having a first side and a second side, where the first side carries the electronic elements. The first side of the electronic circuit component is positioned into contact with the tacky layer. A bonding material is then deposited to a portion of the adhesive layer that is not covered by the first side of the electronic circuit component, to a depth which is sufficient to cover at least a portion of the electronic circuit component. The bonding material is then fixed or cured into a fixed or cured bonding material, and the tacky layer is removed. By these operations, the electronic circuit component is held in a secure attachment by the fixed or cured bonding material, and circuit connections may be made.

    Complex stress-engineered frangible structures
    5.
    发明授权
    Complex stress-engineered frangible structures 有权

    公开(公告)号：US10202990B2

    公开(公告)日：2019-02-12

    申请号：US16025573

    申请日：2018-07-02

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting

    IPC: C03C21/00 ,  F16B1/00 ,  C03B27/00 ,  C03C27/10 ,  C03C27/06 ,  B32B17/00 ,  C03C27/04 ,  C03C15/00 ,  C03B23/203 ,  C03B23/20 ,  B32B17/10

    Abstract: A stress-engineered frangible structure includes multiple discrete glass members interconnected by inter-structure bonds to form a complex structural shape. Each glass member includes strengthened (i.e., by way of stress-engineering) glass material portions that are configured to transmit propagating fracture forces throughout the glass member. Each inter-structure bond includes a bonding member (e.g., glass-frit or adhesive) connected to weaker (e.g., untreated, unstrengthened, etched, or thinner) glass member region(s) disposed on one or both interconnected glass members that function to reliably transfer propagating fracture forces from one glass member to other glass member. An optional trigger mechanism generates an initial fracture force in a first (most-upstream) glass member, and the resulting propagating fracture forces are transferred by way of inter-structure bonds to all downstream glass members. One-way crack propagation is achieved by providing a weaker member region only on the downstream side of each inter-structure bond.

    Stressed Substrates For Transient Electronic Systems
    8.
    发明申请
    Stressed Substrates For Transient Electronic Systems 有权
    用于瞬态电子系统的强化衬底

    公开(公告)号：US20150102852A1

    公开(公告)日：2015-04-16

    申请号：US14052348

    申请日：2013-10-11

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Scott J. H. Limb ,  Gregory L. Whiting ,  Sean R. Garner ,  JengPing Lu ,  Dirk DeBruyker

    IPC: H03K19/177

    CPC classification number: H03K19/17768 ,  H01L21/64 ,  H01L21/71 ,  H01L23/14 ,  H01L23/57 ,  H01L27/00 ,  H01L27/12 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

    Abstract translation: 用于瞬态电子系统的应力衬底（即，当触发时视觉消失的电子系统）包括一个或多个以显着的内部应力的形式存储势能的应力设计层。 还提供了一种相关联的触发机构，其在被触发时引起应力基底中的初始断裂，由此断裂能几乎瞬时地穿过受压基底，导致受应力的基底碎裂成多个小（例如，微米级） 这很难发现。 通过与玻璃回火（例如通过热或化学处理）相似的策略，或者通过沉积具有大量应力的薄膜层，将内部应力结合到受压基板中。 可选地提供图案化的断裂特征以控制最终的断裂的粒度。 在基板上构建的电子系统在瞬态事件期间被完全破坏和分散。

    MICROCHIP CHARGE PATTERNING
    9.
    发明公开
    MICROCHIP CHARGE PATTERNING 审中-公开

    公开(公告)号：US20230187373A1

    公开(公告)日：2023-06-15

    申请号：US18164070

    申请日：2023-02-03

    Applicant: Palo Alto Research Center Incorporated

    Inventor： Eugene M. Chow ,  JenPing Lu ,  Armin R. Volkel ,  Bing R. Hsieh ,  Gregory L. Whiting ,  Sean E. Doris

    IPC: H01L23/544 ,  H01L23/00

    CPC classification number: H01L23/544 ,  H01L24/95 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2224/95085 ,  H01L2224/95145 ,  H01L2924/10253 ,  H01L2924/10329

    Abstract: A method of forming a charge pattern on a microchip includes depositing a first material on an insulator surface of the microchip, depositing a material having capability of forming a self-assembled monolayer on the other material, wherein the material comprises at least one material selected from the group consisting of: octadecyltrichlorosilane, phenethyltrichlorosilane, hexamethyldisilazane, allyltrimethoxysilane, or perfluorooctyltrichlorosilanem, and patterning the self-assembled monolayer to reveal a portion of the first material. A method of forming a charge pattern in a microchip includes depositing a first material as one of either a solution processed material or a vapor deposited material to generate a first polarity or first magnitude of charge, depositing a second material as a vapor deposited material to generate a second polarity or second magnitude of charge, and immersing the microchip in a non-polar fluid comprising one selected from the group consisting of: an isoparafinnic liquid, a hydrocarbon liquid and dodecane.

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