Rational Decision-Making Tool for Semiconductor Processes

    公开(公告)号:US20220327268A9

    公开(公告)日:2022-10-13

    申请号:US17303666

    申请日:2021-06-04

    IPC分类号: G06F30/33 G06N20/00 G06Q30/02

    摘要: A robust predictive model. A plurality of different predictive models for a target feature are run, and a comparative analysis provided for each predictive model that meet minimum performance criteria for the target feature. One of the predictive models is selected, either manually or automatically, based on predefined criteria. For semi-automatic selection, a static or dynamic survey is generated for obtaining user preferences for parameters associated with the target feature. The survey results will be used to generate a model that illustrates parameter trade-offs, which will be used to finalize the optimal predictive model for the user.

    Rational Decision-Making Tool for Semiconductor Processes

    公开(公告)号:US20210294950A1

    公开(公告)日:2021-09-23

    申请号:US17303666

    申请日:2021-06-04

    IPC分类号: G06F30/33 G06N20/00 G06Q30/02

    摘要: A robust predictive model. A plurality of different predictive models for a target feature are run, and a comparative analysis provided for each predictive model that meet minimum performance criteria for the target feature. One of the predictive models is selected, either manually or automatically, based on predefined criteria. For semi-automatic selection, a static or dynamic survey is generated for obtaining user preferences for parameters associated with the target feature. The survey results will be used to generate a model that illustrates parameter trade-offs, which will be used to finalize the optimal predictive model for the user.

    Semiconductor yield prediction
    9.
    发明授权

    公开(公告)号:US11022642B2

    公开(公告)日:2021-06-01

    申请号:US16112278

    申请日:2018-08-24

    摘要: A method for predicting yield for a semiconductor process. A particular type of wafer is fabricated to have a first set of features disposed on the wafer, with a wafer map identifying a location for each of the first set of features on the wafer. Data from wafer acceptance tests and circuit probe tests is collected over time for wafers of that particular type as made in a semiconductor fabrication process, and at least one training dataset and a least one validation dataset are created from the collected data. A second set of “engineered” features are created and also incorporated onto the wafer and wafer map. Important features from the first and second sets of features are identified and selected, and using those important features as inputs, a number of different process models are run, with yield as the target. The results of the different models can be combined, for example, statistically.