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    LOW-POWER BANDGAP REFERENCE VOLTAGE GENERATOR USING LEAKAGE CURRENT
    1.
    发明申请
    LOW-POWER BANDGAP REFERENCE VOLTAGE GENERATOR USING LEAKAGE CURRENT 有权
    低功率带式参考电压发生器使用泄漏电流

    公开(公告)号：US20160334826A1

    公开(公告)日：2016-11-17

    申请号：US15150564

    申请日：2016-05-10

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Jong Mi LEE ,  Young Woo JI

    IPC: G05F3/08

    CPC classification number: G05F3/08

    Abstract: A low-power bandgap reference voltage generator using a leakage current may include: a medium voltage generation unit configured to generate a medium voltage based on the absolute temperature, using a leakage current; a low power amplifier configured to amplify the medium voltage and outputting an operational amplification voltage; and a reference voltage output unit configured to output a reference voltage based on the operational amplification voltage at a target level.

    Abstract translation: 使用漏电流的低功率带隙参考电压发生器可以包括：中压生成单元，被配置为使用泄漏电流基于绝对温度产生中压; 低功率放大器，被配置为放大所述中压并输出运算放大电压; 以及参考电压输出单元，被配置为基于所述运算放大电压在目标电平输出基准电压。

    NEUROMORPHIC SYSTEM WITH TRANSPOSABLE MEMORY AND VIRTUAL LOOK-UP TABLE
    3.
    发明申请
    NEUROMORPHIC SYSTEM WITH TRANSPOSABLE MEMORY AND VIRTUAL LOOK-UP TABLE 审中-公开

    公开(公告)号：US20190279079A1

    公开(公告)日：2019-09-12

    申请号：US16276452

    申请日：2019-02-14

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Hwa Suk CHO ,  Hyun Woo SON

    IPC: G06N3/063 ,  G06N3/08 ,  G06N20/00 ,  G06F1/03

    Abstract: Provided is a technology for reducing hardware cost and enabling on-chip learning in a neuromorphic system. A synapse array includes a plurality of synapse circuits, and at least one of the plurality of synapse circuits includes at least bias transistor and a switch connected in series. Synapse circuits in the same row and column direction of the synapse array are connected to each other through a shared membrane line, and a charge amount proportional to a multiplication accumulation operation required for a forward or backward operation is supplied through the membrane line and is converted into a final digital value for output through an analog to digital converter. A virtual look-up table performs in advance a calculation required for a synapse weight update for learning of at least one column of the synapse array and is updated, so that the amount of a calculation required for entire learning is reduced.

    SAR-TYPE ANALOG-DIGITAL CONVERTER USING RESIDUE INTEGRATION
    6.
    发明申请
    SAR-TYPE ANALOG-DIGITAL CONVERTER USING RESIDUE INTEGRATION 审中-公开

    公开(公告)号：US20190097648A1

    公开(公告)日：2019-03-28

    申请号：US15993432

    申请日：2018-05-30

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Seungnam CHOI

    IPC: H03M3/00

    Abstract: The present invention relates to a successive approximation register (SAR)-type analog-digital converter (ADC), which can amplify a residual voltage without a non-linearity problem caused by an output voltage of a residual voltage amplifier, thereby performing high-resolution analog-digital conversion at low power consumption.The SAR-type ADC may include: a coarse/fine SAR conversion unit configured to receive an analog input voltage and convert the received voltage into an MSB digital signal in a coarse SAR conversion mode, and receive a feedback voltage and convert the received voltage into an LSB digital signal in a fine SAR conversion mode; and a residue integration unit configured to repeatedly amplify a residual voltage with a predetermined gain by a predetermined number of times and output the amplified voltage as a final target multiple, the residual voltage corresponding to a voltage difference between the analog input voltage and an analog voltage obtained by converting the digital signal into an analog signal.

    ALL DIGITAL PHASE LOCKED LOOP
    7.
    发明申请
    ALL DIGITAL PHASE LOCKED LOOP 审中-公开

    公开(公告)号：US20180183447A1

    公开(公告)日：2018-06-28

    申请号：US15795703

    申请日：2017-10-27

    Applicant: SK hynix Inc. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Min Seob LEE ,  In Hwa JUNG ,  Yong Ju KIM

    IPC: H03L7/099 ,  H03L7/07

    CPC classification number: H03L7/0992 ,  H03L7/07

    Abstract: An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

    SYNAPSE CIRCUIT AND NEUROMORPHIC SYSTEM INCLUDING THE SAME
    8.
    发明申请
    SYNAPSE CIRCUIT AND NEUROMORPHIC SYSTEM INCLUDING THE SAME 有权
    包括其中的SYNPSE电路和神经系统

    公开(公告)号：US20140358834A1

    公开(公告)日：2014-12-04

    申请号：US14213368

    申请日：2014-03-14

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION ,  SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jun Seok KIM ,  Jae Yoon SIM ,  Hyun Surk RYU

    IPC: G06N3/08

    CPC classification number: G06N3/049 ,  G06N3/0635 ,  G11C11/54 ,  G11C13/0007 ,  G11C2213/79

    Abstract: A synapse circuit to perform spike timing dependent plasticity (STDP) operation is provided. The synapse circuit includes a memristor having a resistance value, a transistor connected to the memristor, and the transistor configured to receive at least two input signals. The resistance value of the memristor is changed based on a time difference between the at least two input signals received by the transistor.

    Abstract translation: 提供了执行尖峰时序依赖可塑性（STDP）操作的突触电路。 突触电路包括具有电阻值的忆阻器，连接到忆阻器的晶体管，以及被配置为接收至少两个输入信号的晶体管。 基于由晶体管接收的至少两个输入信号之间的时间差来改变忆阻器的电阻值。

    PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER
    10.
    发明申请
    PHASE LOCKED LOOP USING DIRECT DIGITAL FREQUENCY SYNTHESIZER 审中-公开

    公开(公告)号：US20200026323A1

    公开(公告)日：2020-01-23

    申请号：US16474524

    申请日：2017-11-30

    Applicant: POSTECH ACADEMY-INDUSTRY FOUNDATION

    Inventor： Jae Yoon SIM ,  Hwa Suk CHO

    IPC: G06F1/03 ,  H03L7/081 ,  H03L7/083 ,  H03L7/197

    Abstract: The present invention relates to a design technology of a phase locked loop (PLL) for generating an accurate clock frequency in a clock synchronization system.The present invention suggests a new structure based on a hardware description language (HDL), and thus reduces a chip area of a frequency synthesizer while obtaining a wide frequency operation range.Furthermore, since only the HDL is used, the entire frequency synthesizer becomes all-synthesizable, and auto layout (auto P&R) can be achieved through a tool, which makes it possible to reduce a design cost of a designer.

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