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    Apparatus and process for sampling a serial digital signal
    1.
    发明授权
    Apparatus and process for sampling a serial digital signal 失效
    串行数字信号采样的装置和处理

    公开(公告)号：US5848109A

    公开(公告)日：1998-12-08

    申请号：US510458

    申请日：1995-08-02

    申请人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    发明人： Roland Marbot ,  Jean-Claude Le Bihan ,  Andrew Cofler ,  Anne Pierre Duplessix ,  Pascal Couteaux ,  Reza Nezamzadeh-Moosavi

    IPC分类号： H04L7/00 ,  H04L7/033 ,  H03B3/04

    CPC分类号： H04L7/0337 ,  H04L7/0029

    摘要： A process and apparatus for sampling a serial digital signal (D), which includes phasing of the digital signal with a clock signal (C) and sampling the digital signal at delayed instants (Si), wherein the phasing is carried out in reference to the sampling instants. The phasing includes determining phasing test instants (Pi) which refer to the sampling instants (Si) to verify whether transitions of the digital signal are leading or lagging in phase relative to the phasing test instants. The determination of the phasing test instants is achieved by adding to each sampling instant (Si) a delay Y=kR/2, in which k is a positive whole odd number other than zero and R designates a pulse repetition period of the bits of the digital signal (D). The invention has particular utility in data processing and remote data processing systems, and to telecommunication systems.

    摘要翻译： 一种用于对串行数字信号（D）进行采样的处理和装置，其包括用时钟信号（C）对数字信号进行定相并在延迟时刻（Si）对数字信号进行采样，其中定相参照 抽样时刻。 定相包括确定参考采样时刻（Si）的相位测试时刻（Pi），以验证数字信号的转换是相对于定相测试时刻是在前进还是相位滞后。 定相测试时刻的确定是通过将​​延迟Y = kR / 2加到每个采样时刻（Si）来实现的，其中k是除零之外的正整数奇数，R表示 数字信号（D）。 本发明在数据处理和远程数据处理系统以及电信系统中具有特别的用途。

    Device for testing dynamic characteristics of components using serial transmissions
    2.
    发明授权
    Device for testing dynamic characteristics of components using serial transmissions 有权
    使用串行传输测试组件的动态特性的设备

    公开(公告)号：US06476615B1

    公开(公告)日：2002-11-05

    申请号：US09258476

    申请日：1999-02-26

    申请人： Roland Marbot ,  Pascal Couteaux ,  Reza Nezamzadeh

    发明人： Roland Marbot ,  Pascal Couteaux ,  Reza Nezamzadeh

    IPC分类号： G01R2302

    CPC分类号： G01R31/30

    摘要： A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal. The testing device can be used with circuits operating at frequencies in the range of 100 MHz. A method of testing dynamic characteristics of an electronic circuit using a testing device is also provided.

    摘要翻译： 一种用于测试使用串行传输的电子电路的动态特性的测试装置。 该电路包括多路复用装置和用于在组件或电路中实现串行链路的解复用装置。 测试装置包括用于将二进制信号发送到多路复用装置的发射机，用于从解复用装置接收二进制信号的接收机以及用于选择性地提供发射机和接收机之间的耦合的链路。 此外，时钟发生器向发射机提供第一时钟信号，并向接收机提供具有与第一时钟信号不同的频率的第二时钟信号。 在一个优选实施例中，时钟发生器包括单个可编程频率振荡器和可变延迟电路。 可编程频率振荡器提供第一时钟信号，并且可变延迟电路延迟第一时钟信号以递送第二时钟信号。 测试装置可以与在100 MHz范围内工作的电路一起使用。 还提供了使用测试装置测试电子电路的动态特性的方法。

    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate
    4.
    发明授权
    Exclusive-or logic gate with four two-by-two complementary inputs and two complementary outputs, and frequency multiplier incorporating said gate 有权
    具有四个二乘互补输入和两个互补输出的独占逻辑门，以及并入所述门的倍频器

    公开(公告)号：US6137309A

    公开(公告)日：2000-10-24

    申请号：US159316

    申请日：1998-09-23

    申请人： Pascal Couteaux ,  Roland Marbot

    发明人： Pascal Couteaux ,  Roland Marbot

    IPC分类号： H03K5/00 ,  H03K19/21

    CPC分类号： H03K19/215 ,  H03K5/00006

    摘要： An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

    摘要翻译： 具有四个二乘互补输入和两个互补输出的异或逻辑门。 据说这种异或门的结构是对称的，因为门的传播时间是相同的，两对互补输入中的任何一个都被切换，无论输出的转换的性质如何， 该对输入不切换。 所公开的装置能够通过消除某些节点的浮动特性来进一步减少通过门传播信号边缘所花费的时间差异。 它还涉及包括诸如此类的异或门树的倍频器。

    Synchronized communication between integrated circuit chips
    6.
    发明授权
    Synchronized communication between integrated circuit chips 有权
    集成电路芯片之间的同步通信

    公开(公告)号：US07231538B2

    公开(公告)日：2007-06-12

    申请号：US10702042

    申请日：2003-11-06

    申请人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    发明人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    IPC分类号： G06F1/12 ,  G06F13/42

    CPC分类号： G06F1/12 ,  G06F1/10

    摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

    摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。

    Latency Adjustment Between Integrated Circuit Chips
    7.
    发明申请
    Latency Adjustment Between Integrated Circuit Chips 有权
    集成电路芯片之间的延迟调整

    公开(公告)号：US20070045789A1

    公开(公告)日：2007-03-01

    申请号：US11553532

    申请日：2006-10-27

    申请人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    发明人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    IPC分类号： H01L23/495

    CPC分类号： G06F1/12 ,  G06F1/10

    摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

    摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。

    Synchronized communication between integrated circuit chips
    9.
    发明申请
    Synchronized communication between integrated circuit chips 有权
    集成电路芯片之间的同步通信

    公开(公告)号：US20050102545A1

    公开(公告)日：2005-05-12

    申请号：US10702042

    申请日：2003-11-06

    申请人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    发明人： Jean-Paul Clavequin ,  Pascal Couteaux ,  Philippe Diehl

    IPC分类号： G06F1/10 ,  G06F1/12

    CPC分类号： G06F1/12 ,  G06F1/10

    摘要： In emulation systems having a plurality of chips, data communicated between the chips needs to be synchronized. A receiver chip may push or pull on incoming data from an emitter chip in order to synchronize it with a receiver clock. Unexpected latency on the link between the emitter and receiver chips may also be adjusted for.

    摘要翻译： 在具有多个芯片的仿真系统中，在芯片之间通信的数据需要同步。 接收器芯片可以推送或拉出来自发射器芯片的输入数据，以便与接收机时钟同步。 也可以调整发射器和接收器芯片之间的链路上的意外延迟。