公开(公告)号：US06897148B2

公开(公告)日：2005-05-24

申请号：US10410929

申请日：2003-04-09

申请人： Patrick A. Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick A. Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

摘要翻译： 在包括半导体衬底（110）的晶片（104）中形成通孔（114）。 种子层（610）溅射在晶片的底表面上。 种子不会沉积在邻近晶片顶表面的通孔的侧壁上。 导体（810）电镀到通孔中。 在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。 干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。 在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。 通过化学镀在底部形成种子（610）。 导体（810）电镀在种子上。 在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。 非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。 用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。 通过化学镀在底部形成种子（610）。 非保形层可以通过电镀形成。 可以通过电镀沉积钽，然后阳极氧化。 还提供了其他实施例。

公开(公告)号：US07521360B2

公开(公告)日：2009-04-21

申请号：US11548053

申请日：2006-10-10

申请人： Patrick A. Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick A. Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

摘要翻译： 在包括半导体衬底（110）的晶片（104）中形成通孔（114）。 种子层（610）溅射在晶片的底表面上。 种子不会沉积在邻近晶片顶表面的通孔的侧壁上。 导体（810）电镀到通孔中。 在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。 干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。 在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。 通过化学镀在底部形成种子（610）。 导体（810）电镀在种子上。 在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。 非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。 用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。 通过化学镀在底部形成种子（610）。 非保形层可以通过电镀形成。 可以通过电镀沉积钽，然后阳极氧化。 还提供了其他实施例。

公开(公告)号：US20070128868A1

公开(公告)日：2007-06-07

申请号：US11548053

申请日：2006-10-10

申请人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

摘要翻译： 在包括半导体衬底（110）的晶片（104）中形成通孔（114）。 种子层（610）溅射在晶片的底表面上。 种子不会沉积在邻近晶片顶表面的通孔的侧壁上。 导体（810）电镀到通孔中。 在另一个实施例中，通过干膜抗蚀剂掩模（1110）将种子沉积在晶片的开口中。 干膜抗蚀剂突出于开口的边缘，因此种子不会沉积在邻近晶片顶表面的开口的侧壁上。 在另一个实施例中，电介质（120）通过非接触式物理气相沉积（PVD）工艺在半导体衬底（110）的开口中形成，该方法将电介质沉积在侧壁上而不是开口的底部。 通过化学镀在底部形成种子（610）。 导体（810）电镀在种子上。 在另一个实施例中，电介质（2910）形成在开口中以覆盖开口的整个表面。 非共形层（120）通过PVD沉积在侧壁上而不是开口的底部。 用非保形层（120）作为掩模将电介质（2910）从底部蚀刻掉。 通过化学镀在底部形成种子（610）。 非保形层可以通过电镀形成。 可以通过电镀沉积钽，然后阳极氧化。 还提供了其他实施例。

公开(公告)号：US20050170647A1

公开(公告)日：2005-08-04

申请号：US11055940

申请日：2005-02-10

申请人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

发明人： Patrick Halahan ,  Sam Kao ,  Bosco Lan ,  Sergey Savastiouk ,  Oleg Siniaguine

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53238 ,  H01L2924/0002 ,  Y10S438/977 ,  H01L2924/00012 ,  H01L2924/00

摘要： A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (1110). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric (120) is formed in an opening in a semiconductor substrate (110) by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed (610) is formed on the bottom by electroless plating. A conductor (810) is electroplated on the seed. In another embodiment, a dielectric (2910) is formed in the opening to cover the entire surface of the opening. A non-conformal layer (120) is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric (2910) is etched off the bottom with the non-conformal layer (120) as a mask. A seed (610) is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

公开(公告)号：US06749764B1

公开(公告)日：2004-06-15

申请号：US09713137

申请日：2000-11-14

申请人： Oleg Siniaguine ,  Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Oleg Siniaguine ,  Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： B05C300

CPC分类号： H01J37/32761 ,  H01L21/6838

摘要： An article which is being processed with plasma is moved during plasma processing so that the motion of the article comprises at least a first rotational motion, a second rotational motion, and a third rotational motion which occur simultaneously. The apparatus that moves the article comprises a first arm rotatable around a first axis, a second arm rotatably attached to the first arm and rotating the article around a second axis, and a rotational mechanism for inducing a rotational motion of the article in addition to, and simultaneously with, the rotation of the first and second arms.

摘要翻译： 正在等离子体处理的制品在等离子体处理期间移动，使得制品的运动包括同时发生的至少第一旋转运动，第二旋转运动和第三旋转运动。 移动物品的装置包括可围绕第一轴线旋转的第一臂，可旋转地附接到第一臂并使制品围绕第二轴线旋转的第二臂，以及用于引起物品的旋转运动的旋转机构， 并且同时具有第一和第二臂的旋转。

公开(公告)号：US20050212127A1

公开(公告)日：2005-09-29

申请号：US11136799

申请日：2005-05-24

申请人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/50 ,  H01L29/40 ,  H01L23/52

CPC分类号： H01L23/49827 ,  H01L21/76898 ,  H01L23/13 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/10126 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

公开(公告)号：US07049170B2

公开(公告)日：2006-05-23

申请号：US10739788

申请日：2003-12-17

申请人： Sergey Savastiouk ,  Patrick B. Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick B. Halahan ,  Sam Kao

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

摘要翻译： 包装衬底（310）包括半导体插入件（120）和至少一个其它中间衬底（110） BT基板。 半导体插入器具有可连接到插入件上方的管芯（124）的第一接触焊盘（136C）和可连接到插入件下方的电路的第二接触焊盘（340）。 在中介层（120）的半导体衬底（140）中形成通孔（330）。 穿过通孔的导电路径将第一接触焊盘（136C）连接到第二接触焊盘（340）。 第二接触垫（340）突出在插入件的底表面上。 这些突出的接触焊盘（340）插入形成在BT基板的顶表面中的通孔（920）中。 通孔提供强大的机械连接，并且便于插入器处理，特别是如果插入件较薄。 在一些实施例中，插入件或管芯（124.1）在顶表面中具有通孔。 将另一个管芯（124.1,124.2）的突出接触焊盘（340.1,34.2）插入到这些通孔中以提供牢固的连接。

公开(公告)号：US20060035416A1

公开(公告)日：2006-02-16

申请号：US11253943

申请日：2005-10-19

申请人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

发明人： Sergey Savastiouk ,  Patrick Halahan ,  Sam Kao

IPC分类号： H01L21/50 ,  H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circuitry below the interposer. Through vias (330) are made in the semiconductor substrate (140) of the interposer (120). Conductive paths going through the through vias connect the first contact pads (136C) to the second contact pads (340). The second contact pads (340) protrude on the bottom surface of the interposer. These protruding contact pads (340) are inserted into vias (920) formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die (124.1) has vias in the top surface. Protruding contact pads (340.1, 340.2) of another die (124.1, 124.2) are inserted into these vias to provide a strong connection.

公开(公告)号：US20050136635A1

公开(公告)日：2005-06-23

申请号：US10798540

申请日：2004-03-10

申请人： Sergey Savastiouk ,  Sam Kao

发明人： Sergey Savastiouk ,  Sam Kao

IPC分类号： H01L23/14 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.

摘要翻译： 通孔（210,210B）形成在基板的表面。 接触焊盘（139,350）的至少一部分位于通孔中。 集成电路结构的接触焊盘（150,340）被插入到通孔中并附着到衬底的接触焊盘（139,350）上。 通孔提供强大可靠的机械和电气连接。 通孔不仅可以暴露衬底中的接触焊盘（350），而且可以暴露周围区域。 焊料（930）比周围区域润湿接触垫，导致更强的焊点和更好的导电性。 或者，接触可以包括多个导电层（910.1,910.2），顶层（910.2）比底层（910.1）更可焊，并且顶层仅覆盖底层的一部分。

公开(公告)号：US07241675B2

公开(公告)日：2007-07-10

申请号：US10798540

申请日：2004-03-10

申请人： Sergey Savastiouk ,  Sam Kao

发明人： Sergey Savastiouk ,  Sam Kao

IPC分类号： H01L21/44

CPC分类号： H01L23/49827 ,  H01L23/13 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/13022 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099

摘要： Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad (350) in the substrate but also a surrounding region. Solder (930) wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (910.1, 910.2), with the top layer (910.2) being more solder wettable than the bottom layer (910.1) and the top layer covering only a portion of the bottom layer.