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    Carry logic design having simplified timing modeling for a field programmable gate array
    1.
    发明授权
    Carry logic design having simplified timing modeling for a field programmable gate array 有权
    进行逻辑设计具有简化的现场可编程门阵列的时序建模

    公开(公告)号：US06847228B1

    公开(公告)日：2005-01-25

    申请号：US10300212

    申请日：2002-11-19

    申请人： Patrick J. Crotty ,  Tao Pi ,  Steven P. Young

    发明人： Patrick J. Crotty ,  Tao Pi ,  Steven P. Young

    IPC分类号： G06F7/507 ,  H03K19/173 ,  G06F7/50

    CPC分类号： G06F7/507 ,  H03K19/1737

    摘要： A configurable logic block (CLB) slice is provided that includes a single path for a carry input signal to propagate through the CLB slice as a carry output signal. This single path includes a multiplexer that is configured to receive the input signals (including the carry input signal) and provides an output signal that can be routed as the carry output signal. A driver circuit can be coupled to the output terminal of the multiplexer, thereby improving the drive of the single path. A separate path is provided in parallel with the first multiplexer path, thereby enabling the carry input signal to be applied to exclusive OR gates within the CLB slice, or to be provided as an intermediate carry output signal. The single path provides a relatively fast and consistent manner of routing the carry input signal through the CLB slice as the carry output signal. The first and second paths accommodate a carry initialization signal as well as an intermediate carry input signal.

    摘要翻译： 提供了可配置逻辑块（CLB）片，其包括用于进位输入信号作为进位输出信号传播通过CLB片的单个路径。 该单路径包括被配置为接收输入信号（包括进位输入信号）并且提供可作为进位输出信号路由的输出信号的多路复用器。 驱动器电路可以耦合到多路复用器的输出端，从而改善单路径的驱动。 提供与第一多路复用器路径并行的单独路径，从而使携带输入信号能够施加到CLB切片内的异或门，或者被提供为中间进位输出信号。 单路提供了一种相对快速和一致的方式，将进位输入信号通过CLB切片作为进位输出信号。 第一和第二路径容纳进位初始化信号以及中间进位输入信号。

    Programmable logic device having heterogeneous programmable logic blocks
    2.
    发明授权
    Programmable logic device having heterogeneous programmable logic blocks 有权
    具有异构可编程逻辑块的可编程逻辑器件

    公开(公告)号：US07046034B2

    公开(公告)日：2006-05-16

    申请号：US11144901

    申请日：2005-06-03

    申请人： Patrick J. Crotty ,  Tao Pi

    发明人： Patrick J. Crotty ,  Tao Pi

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1776 ,  H03K19/17728

    摘要： A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.

    摘要翻译： 具有异构可编程逻辑块的可编程逻辑器件（PLD）。 在一个实施例中，PLD包括耦合到可编程互连电路的可编程互连电路和可编程输入 - 输出电路。 可编程逻辑块的阵列耦合到互连电路。 每个可编程逻辑块包括耦合到互连电路的多个可编程逻辑元件。 每个可编程逻辑元件都是可编程的，以实现一组共同的功能，并且可编程逻辑元件中的至少一个但不是全部可编程以实现一组补充功能。

    FPGA lookup table with transmission gate structure for reliable low-voltage operation
    4.
    发明授权
    FPGA lookup table with transmission gate structure for reliable low-voltage operation 有权
    具有传输门结构的FPGA查找表，可靠的低电压工作

    公开(公告)号：US06667635B1

    公开(公告)日：2003-12-23

    申请号：US10241094

    申请日：2002-09-10

    申请人： Tao Pi ,  Patrick J. Crotty

    发明人： Tao Pi ,  Patrick J. Crotty

    IPC分类号： H03L19173

    CPC分类号： H03K19/17764 ,  H03K17/693 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/1778

    摘要： A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.

    摘要翻译： 用于现场可编程门阵列（FPGA）的查找表（LUT）被设计为在低电压电平下可靠地运行。 低电压LUT使用CMOS传输门而不是未配对的N沟道晶体管来选择一个存储单元输出作为LUT输出信号。 因此，通过栅极不会发生电压降。 虽然该修改显着增加了LUT的总门控数量，但是通过去除当前设计中所需的半锁存器以及通过去除由该修改不必要的初始化电路可以减轻该缺点。 一些实施例包括降低存储器单元和输出端子之间的通路数量的解码器，代价是在穿过解码器的输入路径上增加延迟。

    FPGA lookup table with transmission gate structure for reliable low-voltage operation
    5.
    发明授权
    FPGA lookup table with transmission gate structure for reliable low-voltage operation 有权
    具有传输门结构的FPGA查找表，可靠的低电压工作

    公开(公告)号：US06809552B1

    公开(公告)日：2004-10-26

    申请号：US10693218

    申请日：2003-10-24

    申请人： Tao Pi ,  Patrick J. Crotty

    发明人： Tao Pi ,  Patrick J. Crotty

    IPC分类号： H03K19177

    CPC分类号： H03K19/17764 ,  H03K17/693 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/1778

    摘要： A lookup table (LUT) for a field programmable gate array (FPGA) is designed to operate reliably at low voltage levels. The low-voltage LUT uses CMOS pass gates instead of unpaired N-channel transistors to select one memory cell output as the LUT output signal. Therefore, no voltage drop occurs across the pass gates. While this modification significantly increases the overall gate count of the LUT, this disadvantage can be mitigated by removing the half-latches required in current designs, and by removing initialization circuitry made unnecessary by the modification. Some embodiments include a decoder that decreases the number of pass gates between the memory cells and the output terminal, at the cost of an increased delay on the input paths that traverse the decoder.

    摘要翻译： 用于现场可编程门阵列（FPGA）的查找表（LUT）被设计为在低电压电平下可靠地运行。 低电压LUT使用CMOS传输门而不是未配对的N沟道晶体管来选择一个存储单元输出作为LUT输出信号。 因此，通过栅极不会发生电压降。 虽然该修改显着增加了LUT的总门控数量，但是通过去除当前设计中所需的半锁存器以及通过去除由该修改不必要的初始化电路可以减轻该缺点。 一些实施例包括降低存储器单元和输出端子之间的通路数量的解码器，代价是在穿过解码器的输入路径上增加延迟。

    Programmable logic device having heterogeneous programmable logic blocks
    6.
    发明授权
    Programmable logic device having heterogeneous programmable logic blocks 有权
    具有异构可编程逻辑块的可编程逻辑器件

    公开(公告)号：US06970012B2

    公开(公告)日：2005-11-29

    申请号：US10167339

    申请日：2002-06-10

    申请人： Patrick J. Crotty ,  Tao Pi

    发明人： Patrick J. Crotty ,  Tao Pi

    IPC分类号： H03K19/177 ,  H03R19/173

    CPC分类号： H03K19/1776 ,  H03K19/17728

    摘要： A programmable logic device (PLD) having heterogeneous programmable logic blocks. In one embodiment, the PLD includes programmable interconnect circuitry and programmable input-output circuitry coupled to the programmable interconnect circuitry. An array of programmable logic blocks is coupled to the interconnect circuitry. Each programmable logic block includes a plurality of programmable logic elements coupled to the interconnect circuitry. Each of the programmable logic elements is programmable to implement a common set of functions, and at least one but less than all of the programmable logic elements is programmable to implement a set of supplemental functions.

    摘要翻译： 具有异构可编程逻辑块的可编程逻辑器件（PLD）。 在一个实施例中，PLD包括耦合到可编程互连电路的可编程互连电路和可编程输入 - 输出电路。 可编程逻辑块的阵列耦合到互连电路。 每个可编程逻辑块包括耦合到互连电路的多个可编程逻辑元件。 每个可编程逻辑元件都是可编程的，以实现一组共同的功能，并且可编程逻辑元件中的至少一个但不是全部可编程以实现一组补充功能。

    Dynamic detection of a strobe signal within an integrated circuit
    7.
    发明授权
    Dynamic detection of a strobe signal within an integrated circuit 有权
    集成电路内的选通信号的动态检测

    公开(公告)号：US08270235B2

    公开(公告)日：2012-09-18

    申请号：US12794605

    申请日：2010-06-04

    申请人： Richard W. Swanson ,  Tao Pi

    发明人： Richard W. Swanson ,  Tao Pi

    IPC分类号： G11C7/00

    CPC分类号： G06F13/1689

    摘要： A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

    摘要翻译： 处理选通信号的方法可以包括对从源同步装置接收的选通信号进行过采样，并且确定发送对源同步装置的读请求之间的时间量，并根据过采样检测选通信号的第一脉冲。 该方法还可以包括响应于至少一个后续读取请求来对选通信号进行静噪的时间量。

    Strobe signal management to clock data into a system
    8.
    发明授权
    Strobe signal management to clock data into a system 有权
    频闪信号管理将数据记录到系统中

    公开(公告)号：US08446195B2

    公开(公告)日：2013-05-21

    申请号：US12794530

    申请日：2010-06-04

    申请人： Richard W. Swanson ,  Tao Pi

    发明人： Richard W. Swanson ,  Tao Pi

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0814 ,  G06F13/1689 ,  G11C7/1093 ,  G11C8/18

    摘要： A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the source synchronous device. Pulses in the strobe signal can be counted. Responsive to detecting a last pulse of the expected number of pulses of the strobe signal, the strobe signal can be replaced with a reference signal that is phase and frequency aligned with the strobe signal.

    摘要翻译： 与源同步装置通信的方法可以包括：响应于针对源同步装置的第一读取请求并从源同步装置接收选通信号，确定要接收的选通信号的预期脉冲数。 可以计数选通信号中的脉冲。 响应于检测选通信号的期望脉冲数的最后脉冲，可以用与选通信号相位和频率对准的参考信号替换选通信号。

    Structure for the main oscillator of a counter-controlled delay line
    9.
    发明授权
    Structure for the main oscillator of a counter-controlled delay line 有权
    反控制延时线主振荡器的结构

    公开(公告)号：US07477112B1

    公开(公告)日：2009-01-13

    申请号：US11505696

    申请日：2006-08-16

    申请人： Tao Pi ,  Alireza S. Kaviani ,  Robert M. Ondris

    发明人： Tao Pi ,  Alireza S. Kaviani ,  Robert M. Ondris

    IPC分类号： H03B27/00

    CPC分类号： H03K5/131 ,  H03K3/0315 ,  H03K2005/00058 ,  H03K2005/00247 ,  H03L7/0814

    摘要： A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.

    摘要翻译： 反向控制的延迟线包括用于延迟输入信号的边沿以产生主时钟信号的主振荡器。 主振荡器包括以环形连接的多个门控延迟元件。 每个门控延迟元件包括用于接收相应的负载信号的第一控制端子，并且包括用于接收释放信号的第二控制端子。 释放信号可以同时启用和禁用所有延迟元件中的状态转换，并且负载信号可以同时将每个延迟元件的输出驱动到任何选择的逻辑状态。

    DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT
    10.
    发明申请
    DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT 有权
    在集成电路中的动态信号的动态检测

    公开(公告)号：US20110299347A1

    公开(公告)日：2011-12-08

    申请号：US12794605

    申请日：2010-06-04

    申请人： Richard W. Swanson ,  Tao Pi

    发明人： Richard W. Swanson ,  Tao Pi

    IPC分类号： G11C7/00

    CPC分类号： G06F13/1689

    摘要： A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal according to the oversampling. The method also can include squelching the strobe signal for the amount of time responsive to at least one subsequent read request.

    摘要翻译： 处理选通信号的方法可以包括对从源同步装置接收的选通信号进行过采样，并且确定发送对源同步装置的读请求之间的时间量，并根据过采样检测选通信号的第一脉冲。 该方法还可以包括响应于至少一个后续读取请求来对选通信号进行静噪的时间量。