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1.发明授权Method for self-correcting cache using line delete, data logging, and fuse repair correction 有权使用行删除，数据记录和保险丝修复校正自校正缓存的方法公开(公告)号：US07529997B2
公开(公告)日：2009-05-05
申请号：US11079816
申请日：2005-03-14
申请人： Patrick J. Meaney , William V. Huott , Thomas J. Knips , David J. Lund , Bryan L. Mechtly , Pradip Patel
发明人： Patrick J. Meaney , William V. Huott , Thomas J. Knips , David J. Lund , Bryan L. Mechtly , Pradip Patel
IPC分类号： G01R31/28
CPC分类号： G11C29/44 , G11C11/41 , G11C15/00 , G11C29/4401 , G11C29/789 , G11C2029/0407 , G11C2029/1208
摘要： An apparatus and method for protecting a computer system from array reliability failures uses Array Built-In Self-Test logic along with code and hardware to delete cache lines or sets that are defective, identify corresponding fuse repair values, proactively call home if spare fuses are not available, schedule soft fuse repairs for the next system restart, schedule line deletes at the next restart, store delete and fuse repairs in a table (tagged with electronic serial id, timestamp of delete or ABIST fail event, address, and type of failure) and proactively call home if there were any missed deletes that were not logged. Fuse information can also be more permanently stored into hardware electronic fuses and/or EPROMs. During a restart, previous repairs are able to be applied to the machine so that ABIST will run successfully and previous deletes to be maintained with checking to allow some ABIST failures which are protected by the line deletes to pass.
摘要翻译： 一种用于保护计算机系统免受阵列可靠性故障的装置和方法使用阵列内置自检逻辑以及代码和硬件来删除有缺陷的高速缓存行或集合，识别相应的保险丝修复值，如果备用保险丝为主动式，则主动呼叫家庭 不可用，为下一次重新启动计划软保险丝修复，下次重新启动时计划行删除，在表中存储删除和保险丝修复（标记为电子序列号，删除时间戳或ABIST失败事件，地址和故障类型 ），并且如果有任何未被记录的遗漏的删除事件，则主动呼叫回家。 保险丝信息也可以更加永久地存储在硬件电子保险丝和/或EPROM中。 在重新启动期间，以前的修复可以应用于机器，以便ABIST将成功运行，以前的删除将通过检查进行维护，以允许由删除行保护的一些ABIST故障通过。
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公开(公告)号：US07437626B2
公开(公告)日：2008-10-14
申请号：US11056726
申请日：2005-02-11
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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3.发明申请Efficient Memory Product for Test and Soft Repair of SRAM with Redundancy 失效高效的内存产品用于冗余的SRAM的测试和软修复公开(公告)号：US20080263417A1
公开(公告)日：2008-10-23
申请号：US12164869
申请日：2008-06-30
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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4.发明授权Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy 失效提供灵活的模块化冗余分配方法和设备，用于内置SRAM冗余自检的存储器公开(公告)号：US07219275B2
公开(公告)日：2007-05-15
申请号：US11053631
申请日：2005-02-08
CPC分类号： G11C29/802 , G11C11/41 , G11C29/44
摘要： A method and apparatus for providing flexible modular redundancy allocation for memory built in self test of random access memory with redundancy. The apparatus includes a first redundancy support register that includes inputs for receiving an address of a location in memory under test and data relating to must fix repair elements. The address includes a row and column vector of the location. The first redundancy support register also includes outputs for transmitting the address and data. The apparatus also includes a second redundancy support register including inputs for receiving the address and data from the outputs of the first redundancy support register. Each of the inputs of the second redundancy support register shares a one-to-one correspondence to each of the outputs of the first redundancy support register. The apparatus further includes allocation logic for providing a modular implementation of the first redundancy support register and the second redundancy support register.
摘要翻译： 一种为具有冗余的随机存取存储器的自检中构建的存储器提供灵活的模块冗余分配的方法和装置。 该装置包括第一冗余支持寄存器，其包括用于接收被测存储器中的位置的地址的输入，以及必须修复修复元件的数据。 该地址包括位置的行和列向量。 第一冗余支持寄存器还包括用于发送地址和数据的输出。 该装置还包括第二冗余支持寄存器，其包括用于从第一冗余支持寄存器的输出接收地址和数据的输入。 第二冗余支持寄存器的每个输入与第一冗余支持寄存器的每个输出共享一一对应关系。 该装置还包括用于提供第一冗余支持寄存器和第二冗余支持寄存器的模块化实现的分配逻辑。
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5.发明授权公开(公告)号：US07793173B2
公开(公告)日：2010-09-07
申请号：US12164869
申请日：2008-06-30
IPC分类号： G11C29/00
CPC分类号： G11C29/24 , G11C11/41 , G11C29/44 , G11C2029/0401 , G11C2029/1208 , G11C2029/4402
摘要： Memory array built in self testing utilizing including a simple data history table. The table is used to track failing locations observed during any level of assembly test of processor or logic semiconductor chips where the chips contain SRAM macros with redundant elements for failure relief.
摘要翻译： 使用包括简单数据历史表在内的自检内置阵列。 该表用于跟踪在处理器或逻辑半导体芯片的任何级别的组装测试期间观察到的故障位置，其中芯片包含具有用于故障消除的冗余元件的SRAM宏。
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公开(公告)号：US07076710B2
公开(公告)日：2006-07-11
申请号：US10413613
申请日：2003-04-14
IPC分类号： G01R31/28
CPC分类号： G11C29/20 , G11C29/14 , G11C2029/0405 , G11C2029/3602
摘要： Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.
摘要翻译： 用于测试具有不均匀二进制地址空间的存储器阵列的方法和系统。 测试系统包括用于产生存储器阵列的地址并用于产生和应用数据模式到存储器阵列的测试引擎。 测试引擎具有包括线性寄存器和用于产生不均匀地址的二进制计数器的串联组合的地址生成器。
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7.发明授权Apparatus and method for implementing multiple memory redundancy with delay tracking clock 失效用延迟跟踪时钟实现多重存储冗余的装置和方法公开(公告)号：US07068554B1
公开(公告)日：2006-06-27
申请号：US11054272
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C29/842
摘要： A memory redundancy control apparatus includes a static compare stage configured to compare bits of a requested memory address to corresponding fuse information bits representing a defective memory address. A dynamic stage is configured to receive outputs of the static compare stage, with an output of the dynamic stage being precharged so as to initially deactivate primary subarray decoding circuitry. The dynamic stage is further triggered by a clock signal thereto. Upon activation of the clock signal, the output of the dynamic stage remains precharged whenever a match exists between the requested memory address and the defective memory address, and the output of the dynamic stage is discharged whenever a mismatch exists between the requested memory address and the defective memory address. A delay tracking clock generator is configured to generate a delay tracking clock signal with respect to the dynamic stage, to gate the output of the dynamic stage to spare subarray decoding circuitry, wherein the spare subarray decoding circuitry is activated whenever the output of the dynamic stage remains precharged following activation of the clock signal.
摘要翻译： 存储器冗余控制装置包括静态比较级，其被配置为将请求的存储器地址的比特与表示缺陷存储器地址的相应的熔丝信息比特进行比较。 动态级被配置为接收静态比较级的输出，动态级的输出被预充电，以便最初去激活主子阵列解码电路。 动态级由其时钟信号进一步触发。 在激活时钟信号时，只要在请求的存储器地址和有缺陷的存储器地址之间存在匹配时，动态级的输出保持预充电，并且只要所请求的存储器地址和存储器地址之间存在不匹配，则动态级的输出被放电 有缺陷的内存地址。 延迟跟踪时钟发生器被配置为相对于动态级产生延迟跟踪时钟信号，以将动态级的输出门控到备用子阵列解码电路，其中每当动态级的输出被激活时，备用子阵列解码电路被激活 在激活时钟信号后仍保持预充电。
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公开(公告)号：US07076706B2
公开(公告)日：2006-07-11
申请号：US09841569
申请日：2001-04-24
IPC分类号： G01R31/28
CPC分类号： G06F11/263
摘要： A method for real time capture of the desired failing chip cell diagnostic information from high speed testing of a semiconductor chip with on chip LSSD registers having built in self test functions and a fail trap register, and there is provided a programmable skip fail counter, and a hold and compare function circuit. The programmable skip counter is enabled for initialization to a “record first fail” mode, and then with non-zero values of the skip counter to a “record next fail” mode with scan initialization of the LSSD registers of the semiconductor chip. The diagnostic information for the chip is obtained by collecting data from scanning the circuits of said semiconductor chip for a failing cell for immediate scan-out off-chip at a level of assembly test.
摘要翻译： 一种用于通过具有内置自检功能的片上LSSD寄存器和故障陷阱寄存器的半导体芯片的高速测试来实时捕获所需故障芯片单元诊断信息的方法，并且提供了可编程跳过失败计数器，以及 一个保持和比较功能电路。 可编程跳过计数器用于初始化为“记录第一失败”模式，然后将跳过计数器的非零值设置为具有半导体芯片的LSSD寄存器的扫描初始化的“记录下一个故障”模式。 芯片的诊断信息是通过在组装测试的水平上收集来自扫描半导体芯片的电路的数据，用于在片外立即扫描的故障单元。
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9.发明授权公开(公告)号：US07064990B1
公开(公告)日：2006-06-20
申请号：US11053812
申请日：2005-02-09
IPC分类号： G11C7/00
CPC分类号： G11C29/848
摘要： An apparatus for implementing multiple memory column redundancy within an individual memory array includes a plurality of memory array elements internally partitioned into at least a pair of subcolumn elements. At least one spare memory element is configured at a size corresponding to one of the subcolumn elements. An input redundancy multiplexing stage and an output redundancy multiplexing stage are configured for steering around one or more defective memory array elements, and an input bit decoding stage and an output bit decoding stage are configured for implementing an additional, external multiplexing stage with respect to the input redundancy multiplexing stage and the output redundancy multiplexing stage.
摘要翻译： 用于在单个存储器阵列内实现多个存储器列冗余的装置包括内部划分为至少一对子列元素的多个存储器阵列元件。 至少一个备用存储器元件被配置为与子列元素之一对应的大小。 配置输入冗余多路复用级和输出冗余多路复用级用于围绕一个或多个有缺陷的存储器阵列元件转向，并且输入位解码级和输出位解码级用于实现相对于 输入冗余复用级和输出冗余复用级。
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公开(公告)号：US20090217112A1
公开(公告)日：2009-08-27
申请号：US12035515
申请日：2008-02-22
申请人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
发明人： Joseph Eckelman , Donato O. Forlenza , Orazio P. Forlenza , William J. Hurley , Thomas J. Knips , Gary William Maier , Phong T. Tran
CPC分类号： G11C29/14 , G11C29/12015 , G11C29/56012 , G11C2029/0405
摘要： A method for implementing at speed bit fail mapping of an embedded memory system having ABIST (Array Built In Self Testing), comprises using a high speed multiplied clock which is a multiple of an external clock of an external tester to sequence ABIST bit fail testing of the embedded memory system. Collect store fail data during ABIST testing of the embedded memory system. Perform a predetermined number of ABIST runs before issuing a bypass order substituting the external clock for the high speed multiplied clock. Use the external clock of the tester to read bit fail data out to the external tester.
摘要翻译： 一种用于实现具有ABIST（Array Built In Self Testing阵列）的嵌入式存储器系统的速率位故障映射的方法，包括使用作为外部测试器的外部时钟的倍数的高速倍增时钟来对ABIST位故障测试进行排序 嵌入式内存系统。 在嵌入式存储系统的ABIST测试期间收集存储失败数据。 在发出旁路命令之前，执行预定数量的ABIST运行，将外部时钟替换为高速倍增时钟。 使用测试仪的外部时钟将位故障数据读出外部测试仪。
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