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    Concurrent multitasking in a uniprocessor
    1.
    发明授权
    Concurrent multitasking in a uniprocessor 失效
    在单处理器中并发多任务

    公开(公告)号：US5867725A

    公开(公告)日：1999-02-02

    申请号：US618689

    申请日：1996-03-21

    申请人： Patrick Wai-Wah Fung ,  Sebastian Theodore Ventrone

    发明人： Patrick Wai-Wah Fung ,  Sebastian Theodore Ventrone

    IPC分类号： G06F9/38 ,  G06F9/46

    CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/462

    摘要： A superscalar uniprocessor that performs concurrent multi-task processing is provided. The processor of the present invention maintains a complete set of program address, memory control and general data registers for each task executing concurrently within the microprocessor, allowing independent control of the program flows. Each set of registers are associated with only one task and are utilized by the memory control and execution units to execute the associated task. The processor includes an instruction fetcher and memory management unit that retrieves an instruction from memory for a given task, as directed by the task's address and control registers, and attaches a task tag to the retrieved instruction that identifies that task. The superscalar processor has a plurality of execution units that can execute a plurality of tasks simultaneously, and a dispatch unit that sends a retrieved instruction and its attached task tag to one of the plurality of execution units for execution. The instruction's task tag identifying the task is then associated with any result data that results from the execution of the instruction. The addition of task tag information in the program flow and in the register file provides for process utilization of execution resources simultaneously with, and substantially independently from other processes, thereby substantially enhancing concurrent multitasking in the superscalar uniprocessor.

    摘要翻译： 提供了执行并发多任务处理的超标量单处理器。 本发明的处理器为在微处理器内同时执行的每个任务维护一整套程序地址，存储器控制和通用数据寄存器，从而允许对程序流的独立控制。 每组寄存器仅与一个任务相关联，并被存储器控制和执行单元用于执行相关联的任务。 处理器包括指令读取器和存储器管理单元，其根据任务地址和控制寄存器的指示从给定任务的存储器检索指令，并且将任务标签附加到识别该任务的检索指令中。 超标量处理器具有可以同时执行多个任务的多个执行单元，以及发送单元，其将检索到的指令及其附加的任务标签发送到多个执行单元之一用于执行。 然后，将指令的任务标签识别任务与与指令执行产生的任何结果数据相关联。 在程序流程和寄存器文件中添加任务标签信息提供了与其他进程同时进行并且基本独立于其他进程的执行资源的进程利用，从而大大增强了超标量单处理器中的并发多任务处理。

    Method and system for optimizing code using an optimizing coprocessor
    3.
    发明授权
    Method and system for optimizing code using an optimizing coprocessor 失效
    使用优化协处理器优化代码的方法和系统

    公开(公告)号：US06820254B2

    公开(公告)日：2004-11-16

    申请号：US09681327

    申请日：2001-03-19

    申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F945

    CPC分类号： G06F8/443

    摘要： A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.

    摘要翻译： 数据处理系统包括与系统存储器通信的中央处理单元（CPU）。 在系统内存中，存储了不利用CPU全部功能的旧版代码。 数据处理系统还包括与CPU和系统存储器通信的代码优化协处理器。 代码优化协处理器内的控制逻辑使得代码优化协处理器在CPU执行遗留代码的同时从旧代码生成优化的代码，使得优化的代码根据CPU进行调整。 在代码优化协处理器已经生成了至少一些优化的代码之后，代码优化协处理器使CPU自动利用至少一些优化的代码来代替至少一些遗留代码。

    Stacked voltage rails for low-voltage DC distribution
    4.
    发明授权
    Stacked voltage rails for low-voltage DC distribution 失效
    用于低压直流分配的堆叠电压轨

    公开(公告)号：US06479974B2

    公开(公告)日：2002-11-12

    申请号：US09750884

    申请日：2000-12-28

    申请人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： G05F304

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

    摘要翻译： 一种用于提供片上电压分配和调节的系统和方法。 根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。 至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。 中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS
    5.
    发明申请
    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS 有权
    设计结构包括数字系统中减少噪声的电路

    公开(公告)号：US20090138676A1

    公开(公告)日：2009-05-28

    申请号：US11946096

    申请日：2007-11-28

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/3869

    摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers
    6.
    发明授权
    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers 失效
    数字系统噪声降低时，噪声是由数据寄存器同步引起的

    公开(公告)号：US07463083B2

    公开(公告)日：2008-12-09

    申请号：US11937559

    申请日：2007-11-09

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： H03K5/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Method and apparatus for providing bus arbitrations in a data processing system
    7.
    发明授权
    Method and apparatus for providing bus arbitrations in a data processing system 有权
    用于在数据处理系统中提供总线仲裁的方法和装置

    公开(公告)号：US06944698B2

    公开(公告)日：2005-09-13

    申请号：US10064379

    申请日：2002-07-08

    申请人： W. Riyon Harding ,  Thomas Michael Lepsic ,  Sebastian Theodore Ventrone

    发明人： W. Riyon Harding ,  Thomas Michael Lepsic ,  Sebastian Theodore Ventrone

    IPC分类号： G06F13/362

    CPC分类号： G06F13/362

    摘要： A method and apparatus for providing bus arbitrations in a multiprocessor system is disclosed. A computer system includes a common bus that is shared by multiple cores, such as processors. A history of bus requests for the common bus made by the cores is stored in a bus request history table. In response to bus request made by the cores, the common bus is arbitrated according to information stored in the bus request history table by an arbiter.

    摘要翻译： 公开了一种用于在多处理器系统中提供总线仲裁的方法和装置。 计算机系统包括由诸如处理器的多个核共享的公共总线。 总线请求历史记录表中存储有由核心产生的公共总线的总线请求的历史记录。 响应于核心的总线请求，公共总线根据仲裁器中存储在总线请求历史表中的信息进行仲裁。

    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT
    10.
    发明申请
    DESIGN STRUCTURE FOR MEASUREMENT OF POWER CONSUMPTION WITHIN AN INTEGRATED CIRCUIT 失效
    在集成电路中测量功耗的设计结构

    公开(公告)号：US20090153324A1

    公开(公告)日：2009-06-18

    申请号：US12046501

    申请日：2008-03-12

    申请人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    发明人： Kenneth Joseph Goodnow ,  Clarence Rosser Ogilvie ,  Nitin Sharma ,  Sebastian Theodore Ventrone ,  Charles S. Woodruff

    IPC分类号： G08B21/00

    CPC分类号： G01R31/31721

    摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.

    摘要翻译： 一种用于测量集成电路运行期间消耗的功率的设计结构。 该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的所述功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。