公开(公告)号：US07607031B2

公开(公告)日：2009-10-20

申请号：US11482269

申请日：2006-07-07

申请人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

发明人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

摘要： A computer system includes a first and a second integrated circuit coupled by a communication link. The communication link operates in a power savings mode in which data is not transmitted over the link. Periodically, the communication link enters a training phase in which training patterns are transmitted over the communication link for a predetermined time period. The communication link returns to the power savings mode after the predetermined time period has elapsed. At least one sideband signal, separate from the communication link, and coupled between the first and second integrated circuits, is used to indicate when to enter the training phase from the power savings mode and exit the training phase and return to the power savings mode.

摘要翻译： 计算机系统包括通过通信链路耦合的第一和第二集成电路。 通信链路以省电模式运行，其中数据不通过链路发送。 周期性地，通信链路进入训练阶段，其中通过通信链路在预定时间段内传送训练模式。 在预定时间段过去之后，通信链路返回到省电模式。 与通信链路分离并且耦合在第一和第二集成电路之间的至少一个边带信号用于指示何时从功率节省模式进入训练阶段并退出训练阶段并返回到省电模式。

公开(公告)号：US07617404B2

公开(公告)日：2009-11-10

申请号：US11482211

申请日：2006-07-07

申请人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

发明人： Paul A. Mackey ,  Paul C. Miranda ,  Larry D. Hewitt ,  Jonathan M. Owen

IPC分类号： G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

摘要： A first portion of a communication link is operated in a power savings mode at the same time that a second portion of the communication link is operated in a normal operational mode. For the first portion, a refresh mode is entered from the power savings mode in which one or more training patterns are transmitted over the first portion, while the second portion remains in the normal operational mode. An indication when to activate and deactivate the refresh mode may be sent over the second portion of the communication link. The refresh mode may be periodically entered from the power savings mode based on an interval register specifying the amount of time the communication link should remain in the power savings mode before a refresh occurs. In addition, the amount of time spent in the refresh mode may be programmable.

摘要翻译： 在通信链路的第二部分以正常操作模式操作的同时，通信链路的第一部分以省电模式操作。 对于第一部分，从功率节省模式输入刷新模式，其中在第一部分上发送一个或多个训练模式，而第二部分保持在正常操作模式。 激活和去激活刷新模式的指示可以在通信链路的第二部分上发送。 可以基于指定在刷新发生之前通信链路应该保持在省电模式的时间量的间隔寄存器，从省电模式周期性地进入刷新模式。 此外，在刷新模式下花费的时间量可以是可编程的。

公开(公告)号：US20110283124A1

公开(公告)日：2011-11-17

申请号：US12777657

申请日：2010-05-11

申请人： Alexander Branover ,  Norman M. Hack ,  Maurice B. Steinman ,  John Kalamatianos ,  Jonathan M. Owen

发明人： Alexander Branover ,  Norman M. Hack ,  Maurice B. Steinman ,  John Kalamatianos ,  Jonathan M. Owen

IPC分类号： G06F1/32 ,  G06F12/08

CPC分类号： G06F1/3275 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06F12/0864 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172

摘要： A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.

摘要翻译： 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。

公开(公告)号：US20080288799A1

公开(公告)日：2008-11-20

申请号：US11750365

申请日：2007-05-18

申请人： Alex Branover ,  Frank P. Helms ,  Jonathan M. Owen ,  Kurt Lewchuk ,  Maurice Steinman ,  Paul Mackey

发明人： Alex Branover ,  Frank P. Helms ,  Jonathan M. Owen ,  Kurt Lewchuk ,  Maurice Steinman ,  Paul Mackey

IPC分类号： G06F1/32

CPC分类号： G06F1/3203

摘要： A processor can operate in different power modes. In an active power mode, the processor executes software. In response to receiving a halt indication from the software, hardware at the processor evaluates bus transactions for the processor. If the bus transactions meet a heuristic, hardware places a processor core in a lower power mode, such as a retention mode. Because the bus transactions are evaluated by hardware, rather than by software, and the software is not required to perform handshakes and other protocols to place the processor in the lower power mode, the processor is able to place the processor core into the lower power mode more quickly, thereby conserving power.

摘要翻译： 处理器可以在不同的功率模式下工作。 在有功功率模式下，处理器执行软件。 响应于从软件接收到停止指示，处理器处的硬件评估处理器的总线事务。 如果总线事务满足启发式，则硬件将处理器内核置于较低​​功耗模式下，例如保留模式。 由于总线事务由硬件而不是软件进行评估，并且软件不需要执行握手和其他协议来将处理器置于低功耗模式，处理器能够将处理器内核置于低功耗模式 更快，从而节约电力。

公开(公告)号：US06760838B2

公开(公告)日：2004-07-06

申请号：US09773763

申请日：2001-01-31

申请人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer

发明人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer

IPC分类号： G06F15177

CPC分类号： G06F15/177

摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed. This scheme includes designating a bootstrap processor, locating the boot ROM, establishing the manner in which the devices are interconnected, and defining routing directions for routing communications among the various devices in the computing system.

摘要翻译： 提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对 。 该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。 链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。 如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。 一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。 该方案包括指定引导处理器，定位引导ROM，建立设备互连的方式，以及定义用于在计算系统中的各种设备之间路由通信的路由选择方向。

公开(公告)号：US20110112798A1

公开(公告)日：2011-05-12

申请号：US12623997

申请日：2009-11-23

申请人： Alexander Branover ,  Maurice B. Steinman ,  Jonathan D. Hauke ,  Jonathan M. Owen

发明人： Alexander Branover ,  Maurice B. Steinman ,  Jonathan D. Hauke ,  Jonathan M. Owen

IPC分类号： G21C17/00

CPC分类号： G06F12/0808 ,  G06F1/3203 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13

摘要： A processing node tracks probe activity level associated with its internal caching or memory system. If the probe activity level increases above a threshold probe activity level, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests. After entering the higher performance state in response to the probe activity level being above the threshold probe activity level, the processing nodes returns to a lower performance state in response to a reduction in probe activity. There may be multiple threshold probe activity levels and associated performance states.

摘要翻译： 处理节点跟踪与其内部缓存或存储器系统相关联的探测活动级别。 如果探测器活动级别增加到阈值探测器活动级别以上，则处理节点的性能状态将增加到其当前的性能状态以提供增强的响应探测请求的性能能力。 响应于探测器活动级别高于阈值探测器活动级别而进入更高性能状态之后，处理节点响应于探测活动的减少而返回到较低的性能状态。 可能存在多个阈值探测活动级别和相关的性能状态。

公开(公告)号：US20110078478A1

公开(公告)日：2011-03-31

申请号：US12566930

申请日：2009-09-25

申请人： Alexander Branover ,  Denis Rystsov ,  Maurice B. Steinman ,  Jonathan M. Owen ,  Denis J. Foley

发明人： Alexander Branover ,  Denis Rystsov ,  Maurice B. Steinman ,  Jonathan M. Owen ,  Denis J. Foley

IPC分类号： G06F1/32 ,  G05F1/10

CPC分类号： G06F1/3203 ,  Y02D10/126

摘要： A method for transitioning power states in a device includes designating a first reduced power state as a target power state. A first expected residency for the target power state is determined based on a counting of activity requests associated with the device. The device is transitioned to the target power state responsive to the expected residency satisfying a first predetermined threshold.

摘要翻译： 用于转换设备中的电源状态的方法包括：将第一降低功率状态指定为目标功率状态。 基于对与设备相关联的活动请求的计数来确定目标电力状态的第一预期驻留。 响应于满足第一预定阈值的预期驻留，该设备被转换到目标功率状态。

公开(公告)号：US20090259874A1

公开(公告)日：2009-10-15

申请号：US12100453

申请日：2008-04-10

申请人： Jonathan M. Owen ,  Michael J. Osborn

发明人： Jonathan M. Owen ,  Michael J. Osborn

IPC分类号： G06F1/00

CPC分类号： G01R31/31726 ,  G06F5/06

摘要： A data transfer device transfers data between two clock domains of a data processing device when the data processing device is in a test mode. The data transfer device receives clock signals associated with each clock domain. To transfer data from a first clock domain to a second clock domain the data transfer device identifies transitions of clock signals associated with each clock domain that are sufficiently remote from each other so that data can deterministically be provided by one clock domain and sampled by the other. This ensures that data can be transferred between the clock domains deterministically even when the phase relationship between the clock signals is indeterminate.

摘要翻译： 当数据处理设备处于测试模式时，数据传输设备在数据处理设备的两个时钟域之间传送数据。 数据传输设备接收与每个时钟域相关联的时钟信号。 为了将数据从第一时钟域传送到第二时钟域，数据传输装置识别与每个时钟域相关联的时钟信号的转变，这些时钟信号彼此足够远，从而可以确定性地由一个时钟域提供数据并由其他时钟域采样 。 这确保即使当时钟信号之间的相位关系是不确定的时，数据也可以确定性地在时钟域之间传送。

公开(公告)号：US06721813B2

公开(公告)日：2004-04-13

申请号：US09774148

申请日：2001-01-30

申请人： Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

发明人： Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

IPC分类号： G06F1300

CPC分类号： G06F13/4243

摘要： A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction. The I/O node may dispatch the non-coherent write transaction directed to the host bridge. The host bridge may respond to the non-coherent write transaction by translating the non-coherent write transaction to a coherent write transaction, and dispatching the coherent write transaction to the second processing node. The second processing node may respond to the coherent write transaction by dispatching a target done response directed to the host bridge.

摘要翻译： 提出了一种实现用于跟踪已发布的写入事务进度的系统和方法的计算机系统。 在一个实施例中，计算机系统包括处理子系统和输入/输出（I / O）子系统。 处理子系统包括通过相干通信链路互连的多个处理节点。 每个处理节点可以包括优选执行软件指令的处理器。 I / O子系统包括一个或多个I / O节点。 每个I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 多个处理节点可以包括第一处理节点和第二处理节点，其中第一处理节点包括主机桥，并且其中存储器耦合到第二处理节点。 I / O节点可以生成非相干写事务以在第二处理节点的存储器内存储数据，其中非相干写事务是已发布的写事务。 I / O节点可以调度定向到主桥的非相干写入事务。 主桥可以通过将非相干写事务转换为相干写事务来响应非相干写事务，并将相干写事务分派到第二处理节点。 第二处理节点可以通过调度定向到主桥的目标完成响应来响应相干写事务。

公开(公告)号：US08880831B2

公开(公告)日：2014-11-04

申请号：US13106285

申请日：2011-05-12

申请人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

发明人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

IPC分类号： G06F13/16

CPC分类号： G06F13/1663 ,  G06F13/1689

摘要： A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

摘要翻译： 公开了一种用于训练存储器的读延迟的方法和装置。 存储器控制器包括被配置为将命令传送到存储器的命令FIFO，耦合以从存储器接收数据的数据队列，以及配置为提供表示数据有效的第一时钟信号的周期数的寄存器 。 在启动程序期间，存储器控制器被配置为在经过第一时钟信号的指定数量的周期之后，将由数据队列接收的数据与已知数据模式进行比较。 存储器控制器还被配置为递减第一值，并且如果接收的数据与数据模式匹配，则重复传送和比较。 如果接收的数据与存储器的任何尝试读取的数据模式不匹配，则存储器控制器被配置为将第二值编程到寄存器中。