利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

327 条记录 (耗时 0.026 秒)

    ERROR DETECTION AND CORRECTION CIRCUITRY
    1.
    发明申请
    ERROR DETECTION AND CORRECTION CIRCUITRY 有权
    错误检测和校正电路

    公开(公告)号：US20120221919A1

    公开(公告)日：2012-08-30

    申请号：US13035826

    申请日：2011-02-25

    申请人： Paul B. Ekas ,  David Lewis

    发明人： Paul B. Ekas ,  David Lewis

    IPC分类号： H03M13/29 ,  G06F11/10

    CPC分类号： G06F11/1076 ,  G06F11/10 ,  G06F11/1048 ,  G11C11/412 ,  G11C29/52 ,  G11C2029/0411 ,  H03K19/17768

    摘要： Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

    摘要翻译： 具有存储器电路的集成电路可以包括错误检测电路和纠错电路。 误差检测电路可用于检测存储器电路中的软错误。 错误检测电路可以包括用于执行奇偶校验的逻辑门。 错误检测电路可以具有交织结构以提供交错数据位处理，可以具有减少逻辑门延迟的树结构，并且可以被流水线化以优化性能。 存储器电路可以与交错结构一起加载交错奇偶校验位以提供多位错误检测能力。 奇偶校验位可以使用设计工具预先计算或在设备配置期间计算。 响应于存储器错误的检测，错误校正电路可用于扫描存储器电路的期望部分并校正存储器错误。

    Error detection and correction circuitry
    2.
    发明授权
    Error detection and correction circuitry 有权
    错误检测和校正电路

    公开(公告)号：US08984367B2

    公开(公告)日：2015-03-17

    申请号：US13035826

    申请日：2011-02-25

    申请人： Paul B. Ekas ,  David Lewis

    发明人： Paul B. Ekas ,  David Lewis

    IPC分类号： G11C29/00 ,  G11C29/52 ,  G06F11/10 ,  H03K19/177 ,  G11C11/412 ,  G11C29/04

    CPC分类号： G06F11/1076 ,  G06F11/10 ,  G06F11/1048 ,  G11C11/412 ,  G11C29/52 ,  G11C2029/0411 ,  H03K19/17768

    摘要： Integrated circuits with memory circuitry may include error detection circuitry and error correction circuitry. The error detection circuitry may be used to detect soft errors in the memory circuitry. The error detection circuitry may include logic gates that are used to perform parity checking. The error detection circuitry may have an interleaved structure to provide interleaved data bit processing, may have a tree structure to reduce logic gate delays, and may be pipelined to optimize performance. The memory circuitry may be loaded with interleaved parity check bits in conjunction with the interleaved structure to provide multi-bit error detection capability. The parity check bits may be precomputed using design tools or computed during device configuration. In response to detection of a memory error, the error correction circuitry may be used to scan desired portions of the memory circuitry and to correct the memory error.

    摘要翻译： 具有存储器电路的集成电路可以包括错误检测电路和纠错电路。 误差检测电路可用于检测存储器电路中的软错误。 错误检测电路可以包括用于执行奇偶校验的逻辑门。 错误检测电路可以具有交织结构以提供交错数据位处理，可以具有减少逻辑门延迟的树结构，并且可以被流水线化以优化性能。 存储器电路可以与交错结构一起加载交错奇偶校验位以提供多位错误检测能力。 奇偶校验位可以使用设计工具预先计算或在设备配置期间计算。 响应于存储器错误的检测，错误校正电路可用于扫描存储器电路的期望部分并校正存储器错误。

    Configurable multi-gate switch circuitry
    4.
    发明授权
    Configurable multi-gate switch circuitry 有权
    可配置的多门开关电路

    公开(公告)号：US08804295B2

    公开(公告)日：2014-08-12

    申请号：US12579792

    申请日：2009-10-15

    申请人： David Lewis

    发明人： David Lewis

    IPC分类号： H01H47/26 ,  H01H50/12 ,  H01H57/00 ,  H01L29/788

    CPC分类号： H01H45/14 ,  H01H59/00 ,  H01H59/0009

    摘要： Integrated circuits with configurable multi-gate switch circuitry are provided. The switch circuitry may include switch control circuitry and an array of multi-gate switches. Each multi-gate switch may have first and second terminals, first and second gates, and a metal bridge. The metal bridge is attached to the first terminal. The metal bridge may extend over the gates and may hover above the second terminal in the off state. The metal bridge may have a tip that bends down to physically contact the second terminal in the on state. Switch control circuitry may provide row and column control signals to load desired switch states into the switch array. The switch array may be partitioned into groups of switches that form multiplexers. The multiplexers may be used in programmable circuits such as programmable logic device circuits.

    摘要翻译： 提供了具有可配置的多栅极开关电路的集成电路。 开关电路可以包括开关控制电路和多栅极开关阵列。 每个多栅极开关可以具有第一和第二端子，第一和第二栅极以及金属桥。 金属桥连接到第一个终端。 金属桥可以在门上延伸，并且可以在关闭状态下悬停在第二端子上方。 金属桥可以具有向下弯曲的尖端，以在接通状态下物理地接触第二端子。 开关控制电路可以提供行和列控制信号以将期望的开关状态加载到开关阵列中。 开关阵列可以被划分为形成多路复用器的开关组。 多路复用器可以用于诸如可编程逻辑器件电路的可编程电路中。

    Methods for preparing cannabis and related products
    5.
    发明授权
    Methods for preparing cannabis and related products 失效
    制备大麻及相关产品的方法

    公开(公告)号：US08753696B1

    公开(公告)日：2014-06-17

    申请号：US13652609

    申请日：2012-10-16

    申请人： David Lewis

    发明人： David Lewis

    IPC分类号： A01N65/00

    CPC分类号： A61K36/185 ,  A61K9/007

    摘要： A method for preparing a medical marijuana mixture includes combining prepared medical marijuana and an alkaline substance in a pulverizing device. The alkaline substance may be coconut, cinnamon, or the like. The pulverizing device may be a coffee grinder, a food processor, a blender, or the like. The mixture may optionally include a sweetener, such as sugar, stevia, or the like.

    摘要翻译： 制备医用大麻混合物的方法包括将制备的医用大麻和碱性物质混合在粉碎装置中。 碱性物质可以是椰子，肉桂等。 粉碎装置可以是咖啡研磨机，食品加工机，搅拌机等。 混合物可以任选地包括甜味剂，例如糖，甜叶菊等。

    Filter
    6.
    发明授权
    Filter 有权
    过滤

    公开(公告)号：US08550092B2

    公开(公告)日：2013-10-08

    申请号：US12669463

    申请日：2008-06-27

    申请人： John Roger Sampson ,  David Lewis

    发明人： John Roger Sampson ,  David Lewis

    IPC分类号： A24D3/04

    CPC分类号： A24D3/10 ,  A24D3/0212 ,  A24D3/048 ,  A24D3/063

    摘要： A filter for a cigarette comprises a porous filter rod (3) a material sheet (2) wrapped around the filter rod and a cellulose acetate thread (4) formed from substantially uncrimped cellulose acetate filaments. The cellulose acetate thread is positioned within the filter rod and extends along the central axis of the filter rod.

    摘要翻译： 用于香烟的过滤器包括多孔过滤棒（3）围绕过滤杆缠绕的材料片（2）和由基本上未卷曲的醋酸纤维素丝形成的醋酸纤维素丝线（4）。 醋酸纤维线被定位在过滤杆内，并沿过滤杆的中心轴延伸。

    Merged tristate multiplexer
    8.
    发明授权
    Merged tristate multiplexer 有权
    合并三态多路复用器

    公开(公告)号：US08525557B1

    公开(公告)日：2013-09-03

    申请号：US13289841

    申请日：2011-11-04

    申请人： David Lewis

    发明人： David Lewis

    IPC分类号： G06F1/08

    CPC分类号： H03K19/1737 ,  H03K17/693

    摘要： Various methods and structures related to tristate multiplexer circuits are disclosed. An embodiment provides a selection circuit in which selectively enabled input circuits are coupled to an output circuit through an output enable circuit such that a selected one of the selectively enabled input circuits is operable to provide a pathway for charging and discharging currents used to charge and discharge an output circuit transistor gate. This and other detailed embodiments are described more fully in the disclosure.

    摘要翻译： 公开了与三态多路复用器电路相关的各种方法和结构。 一个实施例提供了一种选择电路，其中有选择地使能的输入电路通过输出使能电路耦合到输出电路，使得所选择的一个有选择地使能的输入电路可操作地提供用于充电和放电的电流用于充电和放电 输出电路晶体管栅极。 在本公开中更全面地描述了这个和其他详细的实施例。

    Integrated circuits with dual-edge clocking
    9.
    发明授权
    Integrated circuits with dual-edge clocking 有权
    具有双边沿时钟的集成电路

    公开(公告)号：US08519763B2

    公开(公告)日：2013-08-27

    申请号：US12814344

    申请日：2010-06-11

    申请人： Ajay K. Ravi ,  David Lewis

    发明人： Ajay K. Ravi ,  David Lewis

    IPC分类号： H03K3/017

    CPC分类号： H03K3/017 ,  G06F1/10 ,  H03K5/1565

    摘要： Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

    摘要翻译： 提供支持双边沿时钟的集成电路。 集成电路可以包括产生方波时钟信号的锁相环。 时钟信号可以通过输入输出引脚从片外设备提供。 时钟信号可以通过时钟分配网络路由，以向本地时钟信号提供脉冲发生器，以在时钟沿上升沿和下降沿产生时钟脉冲。 脉冲发生器可以产生由具有公共脉冲宽度的上升和下降时钟沿触发的时钟脉冲，以获得最佳性能。 时钟网络引入的占空比失真可能被最小化以获得最佳性能。 可以使用自适应占空比失真电路来控制时钟缓冲器的上拉/下拉驱动强度，使得本地时钟信号的高时钟相位大约为半个时钟周期。